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==Overview ==
 
==Overview ==
RISC-V base ISA consists of 31 [[general-purpose registers]] <code>x1-x31</code> which hold integer values. The register <code>x0</code> is hardwired to the [[zero register|constant <code>0</code>]]. There is an additional user-visible [[program counter]] <code>pc</code> register which holds the address of the current instruction. RISC-V does not define a specific subroutine return address link register, but it does suggest that the standard software calling convention should use register <code>x1</code> to store the return address on a call.
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RISC-V base ISA consists of 32 [[general-purpose registers]] <code>x1-x31</code> which hold integer values. The register <code>x0</code> is hardwired to the [[zero register|constant <code>0</code>]]. There is an additional user-visible [[program counter]] <code>pc</code> register which holds the address of the current instruction. RISC-V does not define a specific subroutine return address link register, but it does suggest that the standard software calling convention should use register <code>x1</code> to store the return address on a call.
  
 
The width of those registers are defined by the RISC-V base variant used. That is, for RV32, the registers are 32 [[bits]] wide, for RV64, they are 64 bits, and for RV128, those registers are 128 bit wide.
 
The width of those registers are defined by the RISC-V base variant used. That is, for RV32, the registers are 32 [[bits]] wide, for RV64, they are 64 bits, and for RV128, those registers are 128 bit wide.

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