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{{title|RISC-V}}
 
{{title|RISC-V}}
 
'''RISC-V''' (pronounced ''risk-five'') is a free and open [[instruction set architecture]] that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], but rather to provide a foundation for emerging classes of [[processors]] and [[accelerators]] that require a base ISA on top of which additional functionality can be added.
 
'''RISC-V''' (pronounced ''risk-five'') is a free and open [[instruction set architecture]] that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], but rather to provide a foundation for emerging classes of [[processors]] and [[accelerators]] that require a base ISA on top of which additional functionality can be added.
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[[category:instruction set architectures]]
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[[category:risc-v]]

Revision as of 02:48, 11 December 2017

RISC-V (pronounced risk-five) is a free and open instruction set architecture that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as x86 and ARM, but rather to provide a foundation for emerging classes of processors and accelerators that require a base ISA on top of which additional functionality can be added.