Semiconductor & Computer Engineering
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Difference between revisions of "risc-v"
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'''RISC-V''' (pronounced ''risk-five'') is a free and open [[instruction set architecture]] that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], but rather to provide a foundation for emerging classes of [[processors]] and [[accelerators]] that require a base ISA on top of which additional functionality can be added. | '''RISC-V''' (pronounced ''risk-five'') is a free and open [[instruction set architecture]] that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as [[x86]] and [[ARM]], but rather to provide a foundation for emerging classes of [[processors]] and [[accelerators]] that require a base ISA on top of which additional functionality can be added. | ||
[[category:instruction set architectures]] | [[category:instruction set architectures]] | ||
[[category:risc-v]] | [[category:risc-v]] | ||
Revision as of 03:10, 11 December 2017
RISC-V
Instruction Set Architecture
Instruction Set Architecture
General
Base Variants(base)
Standard Extensions(all)
Topics
- Foundation
- Non-Standard Extensions
- Addressing Modes
- Registers
- Assembly
- Interrupts
- Microarchitectures
RISC-V (pronounced risk-five) is a free and open instruction set architecture that is specifically designed to enable configurability, modularity, and extensibility. RISC-V is not designed to replace prominent ISAs such as x86 and ARM, but rather to provide a foundation for emerging classes of processors and accelerators that require a base ISA on top of which additional functionality can be added.
