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== Architecture ==
== Architecture ==
RISC-V is designed as a ''Base+Extension'' ISA whereby the architecture is broken down into a very minimal base architecture that is required in order to be able to get a full software stack including a full-fledged operating system and additional standard {{risc-v|extensions}} can be implemented when additional functionality is desired.
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There are three RISC-V base instruction called {{risc-v|RV32I}}, {{risc-v|RV64I}}, and {{risc-v|RV128I}}. Those three variations only operate on integers and represent a {{arch|32}}, {{arch|64}}, and {{arch|128}} address space and [[register]] widths (i.e., word size). All RISC-V implementations must include the base {{risc-v|RV32I}} instructions. The two additional variations simply expand the RV32I register width and add a handful of additional data transfer instructions for working with wider words.
[[category:instruction set architectures]]
[[category:instruction set architectures]]

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