Revision history of "renesas/r-car/m1a"

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(cur | prev) 09:40, 21 July 2017‎ BCD (talk | contribs)‎ . . (378 bytes) (+378)‎ . . (Created page with "{{renesas title|R-Car M1A}} {{mpu}} '''R-Car M1A''' is a mid-range performance embedded dual-core SoC for the automotive industry designed by Renesas and introduced in...")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	R-Car M1A - Renesas#package +
base frequency	800 MHz (0.8 GHz, 800,000 kHz) +
core count	2 +
core name	Cortex-A9 + and SH-4A +
core voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
designer	Renesas + and ARM Holdings +
family	R-Car +
first announced	February 16, 2011 +
first launched	June 2012 +
full page name	renesas/r-car/m1a +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	PowerVR SGX540 +
integrated gpu base frequency	200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designer	Imagination Technologies +
integrated gpu execution units	2 +
io voltage	3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv7 + and SuperH +
isa family	ARM + and SuperH +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	4-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	4-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
ldate	June 2012 +
manufacturer	TSMC +
market segment	Embedded +
max memory	1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth	7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) +
max memory channels	2 +
microarchitecture	Cortex-A9 + and SH-4A +
model number	M1A +
name	R-Car M1A +
package	FCBGA-472 +
part number	R8A77781 +
process	40 nm (0.04 μm, 4.0e-5 mm) +
release price	$ 70.00 (€ 63.00, £ 56.70, ¥ 7,233.10) +
series	1st Gen +
supported memory type	DDR2-800 + and DDR3-1066 +
technology	CMOS +
thread count	2 +
word size	32 bit (4 octets, 8 nibbles) +

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