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Difference between revisions of "renesas/r-car/h2"
< renesas‎ | r-car

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|frequency=1,500 MHz
 
|frequency=1,500 MHz
 
|frequency 2=1,000 MHz
 
|frequency 2=1,000 MHz
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|frequency 3=780 MHz
 
|isa=ARMv7
 
|isa=ARMv7
 
|isa family=ARM
 
|isa family=ARM
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|package module 1={{packages/renesas/fcbga-831}}
 
|package module 1={{packages/renesas/fcbga-831}}
 
}}
 
}}
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'''R-Car H2''' is a high-end embedded [[nona-core]] SoC for the automotive industry introduced by [[Renesas]] in early [[2013]]. The H2 incorporates four {{armh|Cortex-A15}} cores operating at 1.5 GHz, four {{armh|Cortex-A7}} cores operating at 1 GHz, and one {{renesas|SH-4A}} core operating at 780 MHz for real-time processing. This SoC incorporates [[Imagination Technologies|Imagination]]'s {{imgtec|PowerVR G6400}} [[GPU]] operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.
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 +
== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A15 § Cache|l2=Cortex-A7 § Cache}}
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{{cache size
 +
|l1 cache=576 KiB
 +
|l1i cache=288 KiB
 +
|l1i break=9x32 KiB
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|l1d cache=288 KiB
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|l1d break=9x32 KiB
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|l2 cache=2.5 MiB
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}}
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 +
== Memory controller ==
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{{memory controller
 +
|type=DDR3-1600
 +
|ecc=No
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|controllers=1
 +
|channels=2
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|width=32 bit
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=5.96 GiB/s
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|bandwidth dchan=11.92 GiB/s
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}}
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== Expansions ==
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* Flash ROM and SRAM, Data bus width: 8 or 16 bits
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* PCI Express2.0 (1 lane)
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* USB 3.0 Host interface × 1 port (wPHY)
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* USB 2.0 Host interface × 3 port (wPHY)
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* SD Host interface × 4 ch (SDXC, UHS-I)
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* Multimedia card interface × 2 ch
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* Serial ATA interface × 2 ch
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* I²C bus interface × 8 ch
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* Serial communication interface (SCIF) × 10 ch
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* Quad serial peripheral interface (QSPI) × 1 ch (for boot)
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* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
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* Ethernet controller (IEEE802.3u, RMII, without PHY)
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 +
== Graphics ==
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{{integrated graphics
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| gpu                = PowerVR G6400
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| designer            = Imagination Technologies
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| execution units    = 1
 +
| max displays        = 2
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| frequency          = 550 MHz
 +
}}
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 +
== Features ==
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{{arm features
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|thumb=No
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|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=Yes
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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}}
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== Block Diagram ==
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::[[File:r-car h2 block.png|750px]]

Revision as of 16:22, 22 July 2017

Template:mpu R-Car H2 is a high-end embedded nona-core SoC for the automotive industry introduced by Renesas in early 2013. The H2 incorporates four Cortex-A15 cores operating at 1.5 GHz, four Cortex-A7 cores operating at 1 GHz, and one SH-4A core operating at 780 MHz for real-time processing. This SoC incorporates Imagination's PowerVR G6400 GPU operating at 550 MHz and supports up to dual-channel DDR3-1600 memory.

Cache

Main articles: Cortex-A15 § Cache and Cortex-A7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$576 KiB
589,824 B
0.563 MiB
L1I$288 KiB
294,912 B
0.281 MiB
9x32 KiB  
L1D$288 KiB
294,912 B
0.281 MiB
9x32 KiB  
L2$2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions

  • Flash ROM and SRAM, Data bus width: 8 or 16 bits
  • PCI Express2.0 (1 lane)
  • USB 3.0 Host interface × 1 port (wPHY)
  • USB 2.0 Host interface × 3 port (wPHY)
  • SD Host interface × 4 ch (SDXC, UHS-I)
  • Multimedia card interface × 2 ch
  • Serial ATA interface × 2 ch
  • I²C bus interface × 8 ch
  • Serial communication interface (SCIF) × 10 ch
  • Quad serial peripheral interface (QSPI) × 1 ch (for boot)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Ethernet controller (IEEE802.3u, RMII, without PHY)

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6400
DesignerImagination Technologies
Execution Units1Max Displays2
Frequency550 MHz
0.55 GHz
550,000 KHz

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension

Block Diagram

r-car h2 block.png
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/h2&oldid=55849"
Facts about "R-Car H2 - Renesas"
RDF feed
has ecc memory supportfalse +
integrated gpuPowerVR G6400 +
integrated gpu base frequency550 MHz (0.55 GHz, 550,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size288 KiB (294,912 B, 0.281 MiB) +
l1i$ size288 KiB (294,912 B, 0.281 MiB) +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
supported memory typeDDR3-1600 +