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Mars II - Microarchitectures - Phytium
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Revision as of 00:42, 19 February 2019 by David (talk | contribs) (Process technology)

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Mars II µarch
General Info
Arch TypeCPU
DesignerPhytium
ManufacturerTSMC
Introduction2019
Process16 nm
Core Configs64
Pipeline
TypeSuperscalar, Pipelined
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
Succession

Mars II is the successor to Mars I, an ARM server SoC microarchitecture designed by Phytium Technology for the Chinese server market.

Process technology

Mars II is largely a shrink of Mars I, from 28 nm process to a 16 nm FinFET process.

Architecture

Key changes from Mars I

  • 16 nm process (from 28 nm)
  • 15% higher frequency (2.3 GHz, up from 2 GHz)
  • -25% lower power (96 W TDP, down from 120 W)
  • Core
    • FTC-662 (from FTC-661/0)
  • System memory
    • DDR4 (from DDR3)
    • Higher data rates (2666 MT/s, up from 1600 MT/s)

This list is incomplete; you can help by expanding it.

Overview

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Die


mars ii die.png


mars ii die (annotated).png


mars ii die 2.png
codenameMars II +
core count64 +
designerPhytium +
first launched2019 +
full page namephytium/microarchitectures/mars ii +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameMars II +
process16 nm (0.016 μm, 1.6e-5 mm) +