From WikiChip
Difference between revisions of "phytium/microarchitectures/mars ii"
< phytium

(SoC)
(Architecture)
Line 31: Line 31:
 
** FTC-662 (from FTC-661/0)
 
** FTC-662 (from FTC-661/0)
 
* System memory
 
* System memory
** [[DDR4]] (from [[DDR3]])
+
** Panel directly connected to 1 MCU (Previously linked to CMC)
** Higher data rates (2400 MT/s, up from 1600 MT/s)
+
*** [[DDR4]] (from [[DDR3]])
 +
*** Higher data rates (2400 MT/s, up from 1600 MT/s)
 
{{expand list}}
 
{{expand list}}
  

Revision as of 19:11, 17 March 2019

Edit Values
Mars II µarch
General Info
Arch TypeCPU
DesignerPhytium
ManufacturerTSMC
Introduction2019
Process16 nm
Core Configs64
Pipeline
TypeSuperscalar, Pipelined
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
Succession

Mars II is the successor to Mars I, an ARM server SoC microarchitecture designed by Phytium Technology for the Chinese server market.

Process technology

Mars II is largely a shrink of Mars I, from 28 nm process to a 16 nm FinFET process.

Architecture

Key changes from Mars I

  • 16 nm process (from 28 nm)
  • 15% higher frequency (2.3 GHz, up from 2 GHz)
    • higher FLOPS performance (588.8 GFLOPS, up from 512 GFLOPS)
  • -25% lower power (96 W TDP, down from 120 W)
  • Core
    • FTC-662 (from FTC-661/0)
  • System memory
    • Panel directly connected to 1 MCU (Previously linked to CMC)
      • DDR4 (from DDR3)
      • Higher data rates (2400 MT/s, up from 1600 MT/s)

This list is incomplete; you can help by expanding it.

Block diagram

Entire SoC

mars ii soc block diagram.svg

Panel

mars ii panel block diagram.svg

Core

Main article: Xiaomi Core

See Xiaomi Core.

Overview

Mars II is Phytium's second-generation many-core server processor based on a custom ARM core. The Mars II is largely a shrink of their first-generation SoC but it does introduce a number of enhancements. Fabricated on a leading-edge 16 nm FinFET process, the new SoC is considerably smaller than the prior die, offers higher frequency, and lower power. Mars II features 64 custom ARMv8.0 cores operating at up to 2.3 GHz for a total of 588.8 GFLOPS. The SoC incorporates high DDR4-2400 memory channels and includes 33 PCIe Gen 3.0 lanes.

Package

PackageFCBGA-3576mars ii fcbga-3576.png
Dimensions61mm x 61mm
Bumps11916
Contacts3576

Die

Panel

mars ii panel.png
mars ii panel (annotated).png

SoC


mars ii die.png


mars ii die (annotated).png


mars ii die 2.png

Bibliography

  • HPC Asia 2019
codenameMars II +
core count64 +
designerPhytium +
first launched2019 +
full page namephytium/microarchitectures/mars ii +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameMars II +
process16 nm (0.016 μm, 1.6e-5 mm) +