Revision as of 01:13, 3 November 2017

Template:mpu PEZY-SC4 (PEZY Super Computer 4) is fifth generation many-core microprocessor planned by PEZY. The SC4 incorporates 16,192 cores, twice times as many cores as its predecessor.

Planned to be fabricated on TSMC's 5 nm process, PEZY-SC5 operates at 1.6 GHz and consume around 640 W while delivering performance in the order of 210 TFLOPS (HP), 105 TFLOPS (SP), and 52.5 TFLOPS (DP).

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Memory controller

For main memory, the PEZY-SC4 supports 4 channels of 64-bit DDR5-4000 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR5-4000 Supports ECC Yes Controllers 4 Channels 4 Width 64 bit Max Bandwidth 119.2 GiB/s 122,060.8 MiB/s 127.99 GB/s 127,990.025 MB/s 0.116 TiB/s 0.128 TB/s Bandwidth Single 29.8 GiB/s Double 59.6 GiB/s Quad 119.2 GiB/s

In addition to main memory bandwidth, the PEZY-SC4 supports Wide-IO with a width of 4,096 bit, twice of the SC3. As with the SC3, the SC4 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 2.8 TiB/s per interface for a total aggregated bandwidth of 22.35 TB/s - twice the bandwidth of its predecessor.

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Memory Wide I/O Rate 3,000 MHz Width 4,096 bit Channels 8 Max Bandwidth 22.35 TiB/s 22,886.4 GiB/s 23,435,673.6 MiB/s 24,574.085 GB/s 24,574,084.881 MB/s 24.574 TB/s

Expansions

With the SC4, PEZY plans to expand on the custom optics interface that was designed for the PEZY-SC3 for up to 512 lanes.