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Revision as of 00:36, 1 November 2017

Template:mpu PEZY-SC4 (PEZY Super Computer 4) is fifth generation many-core microprocessor planned by PEZY. The SC4 incorporates 16,192 cores, twice times as many cores as its predecessor.

Planned to be fabricated on TSMC's 5 nm process, PEZY-SC5 operates at 1.6 GHz and consume around 640 W while delivering performance in the order of 210 TFLOPS (HP), 105 TFLOPS (SP), and 52.5 TFLOPS (DP).


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR5-4000
Supports ECCYes
Controllers4
Channels4
Max Bandwidth119.2 GiB/s
122,060.8 MiB/s
127.99 GB/s
127,990.025 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Quad 119.2 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate3,000 MHz
Width4,096 bit
Channels8
Max Bandwidth22.35 TiB/s
22,886.4 GiB/s
23,435,673.6 MiB/s
24,574.085 GB/s
24,574,084.881 MB/s
24.574 TB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes512
Configsx16, x8, x4
UART

GP I/OYes
Facts about "PEZY-SC4 - PEZY"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
PEZY-SC4 - PEZY#io +
has ecc memory supporttrue + and false +
max memory bandwidth119.2 GiB/s (122,060.8 MiB/s, 127.99 GB/s, 127,990.025 MB/s, 0.116 TiB/s, 0.128 TB/s) + and 22,886.4 GiB/s (23,435,673.6 MiB/s, 24,574.085 GB/s, 24,574,084.881 MB/s, 22.35 TiB/s, 24.574 TB/s) +
max memory channels4 + and 8 +
max pcie lanes512 +
supported memory typeDDR5-4000 +