From WikiChip
PEZY-SC3 - PEZY
< pezy‎ | pezy-scx
Revision as of 01:55, 3 November 2017 by David (talk | contribs)

Template:mpu PEZY-SC3 (PEZY Super Computer 3) is a fourth generation many-core microprocessor developed by PEZY set to be introduced in late 2019. This chip, which is planned to operate at 1.3 GHz, will incorporate 8,192 cores and dissipate 400 W. The PEZY-SC3 will power the ZettaScaler-3.x series of supercomputers.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Overview

The SC3 will be introduced by PEZY along with their third-generation ZettaScaler-3.0 supercomputer series. The SC3 is set to incorporate 8,192 cores along with 8-way SMT support for a total of 65,536 threads, four times as many cores as its predecessor.

Operating at 1.3 GHz, the PEZY-SC3 will have a peak performance of 43.69 TFLOPS (single-precision) and 21.845 TFLOPS (double-precision) while consuming around 400 Watts. The PEZY-SC3 is expected to be manufactured on TSMC's 7 nm process.

Cache

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory controller

For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3600
Supports ECCYes
Controllers4
Channels4
Width64 bit
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 26.82 GiB/s
Double 53.64 GiB/s
Quad 107.3 GiB/s

In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice of the SC2. As with the SC2, the SC3 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate3,000 MHz
Width2,048 bit
Channels8
Max Bandwidth11.18 TiB/s
11,448.32 GiB/s
11,723,079.68 MiB/s
12,292.54 GB/s
12,292,539.999 MB/s
12.293 TB/s

Expansions

With the SC3, PEZY plans to replace the previous PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.

Facts about "PEZY-SC3 - PEZY"
has ecc memory supporttrue + and false +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + and 11,448.32 GiB/s (11,723,079.68 MiB/s, 12,292.54 GB/s, 12,292,539.999 MB/s, 11.18 TiB/s, 12.293 TB/s) +
max memory channels4 + and 8 +
peak flops (double-precision)21,845,333,327,872 FLOPS (21,845,333,327.872 KFLOPS, 21,845,333.328 MFLOPS, 21,845.333 GFLOPS, 21.845 TFLOPS, 0.0218 PFLOPS, 2.184533e-5 EFLOPS, 2.184533e-8 ZFLOPS) +
peak flops (half-precision)87,381,333,311,488 FLOPS (87,381,333,311.488 KFLOPS, 87,381,333.311 MFLOPS, 87,381.333 GFLOPS, 87.381 TFLOPS, 0.0874 PFLOPS, 8.738133e-5 EFLOPS, 8.738133e-8 ZFLOPS) +
peak flops (single-precision)43,690,666,655,744 FLOPS (43,690,666,655.744 KFLOPS, 43,690,666.656 MFLOPS, 43,690.667 GFLOPS, 43.691 TFLOPS, 0.0437 PFLOPS, 4.369067e-5 EFLOPS, 4.369067e-8 ZFLOPS) +
supported memory typeDDR4-3600 +