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Difference between revisions of "pezy/pezy-scx/pezy-sc2"
< pezy‎ | pezy-scx

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{{pezy title|PEZY-SC2}}
 
{{pezy title|PEZY-SC2}}
 
{{mpu
 
{{mpu
| future             = Yes
+
|future=Yes
| name               = PEZY-SC2
+
|name=PEZY-SC2
| no image           = Yes
+
|no image=Yes
| image              =
+
|designer=PEZY
| image size          =
+
|manufacturer=TSMC
| caption            =
+
|model number=PEZY-SC2
| designer           = PEZY
+
|market=Supercomputer
| manufacturer       = TSMC
+
|first announced=2015
| model number       = PEZY-SC2
+
|first launched=2016
| part number        =
+
|frequency=1,000 MHz
| market             = Industrial
+
|process=16 nm
| first announced     = 2015
+
|technology=CMOS
| first launched     = 2016
+
|die area=620 mm²
| last order          =
+
|core count=2,048
| last shipment      =
+
|power=200 W
 
+
|v core=0.8 V
| family              =
+
|electrical=Yes
| series              =
 
| locked              =
 
| frequency           = 999.99 MHz
 
| bus type            =
 
| bus speed          = 66.66 MHz
 
| bus rate            =
 
| clock multiplier    = 15
 
 
 
| microarch          =
 
| platform            =
 
| chipset            =
 
| core name          =
 
| core family        =
 
| core model          =
 
| core stepping      =
 
| process             = 16 nm
 
| transistors        =
 
| technology         = CMOS
 
| die area           = 400-500 mm²
 
| die width          =
 
| die length          =
 
| word size          =
 
| core count         = 4,096
 
| thread count        =
 
| max cpus            =
 
| max memory          =
 
| max memory addr    =
 
 
 
| electrical          = Yes
 
| power               = 100 W
 
| v core             =
 
| v core tolerance    =
 
| v io                =
 
| v io tolerance      =
 
| sdp                =
 
| tdp                =
 
| ctdp down          =
 
| ctdp down frequency =
 
| ctdp up            =
 
| ctdp up frequency  =
 
| temp min            =
 
| temp max            =
 
| tjunc min          = <!-- °C -->
 
| tjunc max          =
 
| tcase min          =
 
| tcase max          =
 
| tstorage min        =
 
| tstorage max        =
 
 
 
| packaging          =  
 
| package 0           =
 
| package 0 type      =
 
| package 0 pins      =
 
| package 0 pitch    =
 
| package 0 width    =
 
| package 0 length    =
 
| package 0 height    =
 
| socket 0            =
 
| socket 0 type      =  
 
 
}}
 
}}
 
'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] set to be released in late 2016 or early 2017. The SC2 is planned to have 4096 cores, 4 times as many cores as its predecessor. Unlike the {{pezy|PEZY-SC}} which had 2 {{armh|ARM926}}, the SC2 will be replaced by 12 {{mips|MIPS64}} cores.
 
'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] set to be released in late 2016 or early 2017. The SC2 is planned to have 4096 cores, 4 times as many cores as its predecessor. Unlike the {{pezy|PEZY-SC}} which had 2 {{armh|ARM926}}, the SC2 will be replaced by 12 {{mips|MIPS64}} cores.

Revision as of 05:12, 23 June 2017

Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY set to be released in late 2016 or early 2017. The SC2 is planned to have 4096 cores, 4 times as many cores as its predecessor. Unlike the PEZY-SC which had 2 ARM926, the SC2 will be replaced by 12 MIPS64 cores.

PEZY-SC2 is planned to operate at 1 GHz and consume around 100 W while delivering performance in the order of 16.4 TFLOPS (single-precision) and 8.2 TFLOPS (double precision). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.