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PEZY-SC - PEZY
< pezy‎ | pezy-scx

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PEZY-SC
pezy-sc (front).png
General Info
DesignerPEZY
ManufacturerTSMC
Model NumberPEZY-SC
MarketSupercomputer
Introduction2013 (announced)
September, 2014 (launched)
General Specs
FamilyPEZY-SCx
Frequency733.33 MHz
Microarchitecture
Process28 nm
Transistors3,730,000,000
TechnologyCMOS
Die411.6 mm²
19.5 mm × 21.1 mm
Cores1,024
Threads8,192
Electrical
Power dissipation100 W
power dissipation (average)70 W
Vcore1.0 V
Packaging
PackageFCBGA-2112 (BGA)pezy-sc (back).png
Dimension47.5 mm x 47.5 mm x 4.05 mm
Pitch1 mm
Contacts2,112

PEZY-SC (PEZY Super Computer) is a second generation many-core microprocessor developed by PEZY and introduced in 2014. This chip, which operates at 733 MHz, incorporates 1,024 cores dissipating 100 W. The PEZY-SC powers the ZettaScaler-1.x series of supercomputers. The PEZY-SC is used in a number of TOP500 & Green500 supercomputers as the world's most efficient supercomputers.

Overview

See also: PEZY-1

The PEZY-SC (SC for "Super Computer") is PEZY's second generation microprocessors which builds upon the PEZY-1. The chip contains exactly twice as many cores and incorporates a large amount of cache including 8 MB of L3$. The chip contains 2 ARM926 cores (ARMv5TEJ) along with 1,024 simpler cores supporting 8-way SMT for a total of 8,192 threads. Operating at 733 MHz, the processor has a peak performance of 3.0 TFLOPS (single-precision) and 1.5 TFLOPS (double-precision). PEZY-SC was designed using 580 million gates and manufactured on TSMC's 28HPC+.

The chip has a peak power dissipation of 100 W with a typical power consumption of 70 W which consists of 10 W leakage + 60 W dynamic.

In June of 2015, PEZY-SC-based supercomputers took all top 3 spots on the Green500 listing as the 3 most efficient supercomputers. PEZY-SC powers Shoubu (1,181,952 cores, ? kW, 605.624 TFlop/s Linpack Rmax), and Suiren Blue (262,656 cores, 40.86 kW, 247.752 TFlop/s Linpack Rmax), and Suiren (328,480 cores, 48.90 kW, 271.782 TFlop/s Linpack Rmax) supercomputers (ranked 1, 2, and 3 respectively).

Architecture

Further information: PEZY-SCx § Architecture

The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 MiB of L3$ enclosed by 16 smaller blocks called "Cities". Each City is made of 64 KiB of L2$, a number of special function units, and 4 smaller blocks called "Villages". A village is a block of 4 execution units. For every 2 execution units there is 2 KiB of L1D$.

pezy-sc arch.svg

Cache

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32 KiB (2x) and 64 KiB L2$ (shared).

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
L1I$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
2x16 KiB  
L1D$32 KiB
0.0313 MiB
32,768 B
3.051758e-5 GiB
2x16 KiB  

L2$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
  1x64 KiB  

The chip integrates a multi-level cache hierarchy:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
L1I$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
1024x2 KiBper processor element 
L1D$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
512x2 KiBper 2 processor elements 

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x2 MiBper citywrite-back

L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiBper prefecture 

Additionally, there is another 16 MiB of scratch-pad memory consisting of 16 KiB per PE.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Controllers8
Channels8
Width64 bit
Max Bandwidth127.156 GiB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/
Hexa 95.37 GiB/s
Octa 127.156 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 2.0
Max Lanes: 32
Configuration: 4x8


Die Shot

pezy sc die shot.jpg


pezy-sc die shot (annotated).png

Floorplan

pezy-sc floorplan.png

External Links

Facts about "PEZY-SC - PEZY"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
PEZY-SC - PEZY#package + and PEZY-SC - PEZY#pcie +
base frequency733.33 MHz (0.733 GHz, 733,330 kHz) +
core count1,024 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerPEZY +
die area411.6 mm² (0.638 in², 4.116 cm², 411,600,000 µm²) +
die length19.5 mm (1.95 cm, 0.768 in, 19,500 µm) +
die width21.1 mm (2.11 cm, 0.831 in, 21,100 µm) +
familyPEZY-SCx +
first announced2013 +
first launchedSeptember 2014 +
full page namepezy/pezy-scx/pezy-sc +
has ecc memory supporttrue +
instance ofmicroprocessor +
l1$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l1d$ descriptionper 2 processor elements +
l1d$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + and 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l1i$ descriptionper processor element +
l1i$ size0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + and 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l2$ descriptionper city +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + and 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ descriptionper prefecture +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateSeptember 2014 +
main imageFile:pezy-sc (front).png +
manufacturerTSMC +
market segmentSupercomputer +
max memory channels8 +
model numberPEZY-SC +
namePEZY-SC +
packageFCBGA-2112 +
peak flops (double-precision)1,501,866,665,984 FLOPS (1,501,866,665.984 KFLOPS, 1,501,866.666 MFLOPS, 1,501.867 GFLOPS, 1.502 TFLOPS, 0.0015 PFLOPS, 1.501867e-6 EFLOPS, 1.501867e-9 ZFLOPS) +
peak flops (single-precision)3,003,733,331,968 FLOPS (3,003,733,331.968 KFLOPS, 3,003,733.332 MFLOPS, 3,003.733 GFLOPS, 3.004 TFLOPS, 0.003 PFLOPS, 3.003733e-6 EFLOPS, 3.003733e-9 ZFLOPS) +
power dissipation100 W (100,000 mW, 0.134 hp, 0.1 kW) +
power dissipation (average)70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
process28 nm (0.028 μm, 2.8e-5 mm) +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8,192 +
transistor count3,730,000,000 +