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Information for "nvidia/tegra/xavier"

Basic information

Display titleTegra Xavier - Nvidia
Default sort keyTegra Xavier, Nvidia
Page length (in bytes)8,660
Page ID27672
Page content languageEnglish (en)
Page content modelwikitext
Indexing by robotsAllowed
Number of redirects to this page12
Counted as a content pageYes
Number of subpages of this page0 (0 redirects; 0 non-redirects)

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Edit history

Page creatorDavid (talk | contribs)
Date of page creation22:15, 9 January 2018
Latest editor199.116.118.167 (talk)
Date of latest edit02:08, 9 December 2019
Total number of edits59
Total number of distinct authors6
Recent number of edits (within past 90 days)0
Recent number of distinct authors0

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Facts about "Tegra Xavier - Nvidia"
core count8 +
core nameCarmel +
designerNvidia +
die area350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) +
familyTegra +
first announcedJanuary 8, 2018 +
first launchedJune 2018 +
full page namenvidia/tegra/xavier +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
ldateJune 2018 +
main imageFile:xavier soc chip.png +
manufacturerTSMC +
market segmentArtificial Intelligence + and Embedded +
max cpu count4 +
max memory bandwidth127.1 GiB/s (221.154 GB/s, 130,150.4 MiB/s, 0.124 TiB/s, 0.137 TB/s) +
max memory channels8 +
microarchitectureCarmel + and Volta +
model numberTegra194 +
nameXavier +
process12 nm (0.012 μm, 1.2e-5 mm) +
smp max ways4 +
supported memory typeLPDDR4X-4266 +
tdp30 W (30,000 mW, 0.0402 hp, 0.03 kW) +
tdp (typical)20 W (20,000 mW, 0.0268 hp, 0.02 kW) +
technologyCMOS +
thread count8 +
transistor count9,000,000,000 +
word size64 bit (8 octets, 16 nibbles) +