== Architecture ==

== Architecture ==

=== CPU ===

=== CPU ===

{{main|nvidia/microarchitectures/carmel|l1=Carmel core}}

{{main|nvidia/microarchitectures/carmel|l1=Carmel core}}

The chip features eight control/management {{nvidia|Carmel|l=arch}} cores, Nvidia's own custom {{arch|64}} [[ARM]] cores. Those cores implement [[ARMv8.2]] with [[RAS]] support and safety built-in, including dual-execution mode. The cluster consists of 4 duplexes, each sharing 2 MiB of L2 cache. All cores are fully [[cache coherent]] which is extended to {{nvidia|Volta|the GPU|l=arch}} and all the other accelerators in the chip. Compared to {{\\|Parker}} which was based on {{nvidia|Denver 2|l=arch}}, Nividia reports around 2x the multithreaded performance.

The chip features eight control/management {{nvidia|Carmel|l=arch}} cores, Nvidia's own custom {{arch|64}} [[ARM]] cores. Those cores implement [[ARMv8.2]] with [[RAS]] support and safety built-in, including dual-execution mode. The cluster consists of 4 duplexes, each sharing 2 MiB of L2 cache. All cores are fully [[cache coherent]] which is extended to {{nvidia|Volta|the GPU|l=arch}} and all the other accelerators in the chip. Compared to {{\\|Parker}} which was based on {{nvidia|Denver 2|l=arch}}, Nividia reports around 2x the multithreaded performance.

=== GPU ===

=== GPU ===

{{main|nvidia/microarchitectures/volta|l1=Volta}}

{{main|nvidia/microarchitectures/volta|l1=Volta}}

Xavier implements a derivative of their {{nvidia|Volta|l=arch}} GPU with a set of finer changes to address the machine learning market, particularly improving inference performance over training. It has eight Volta stream multiprocessors along with their standard 128 KiB of L1 cache and a 512 KiB of shared L2. Compared to Parker, Nvidia claims this GPU has 2.1x the graphics performance. Whereas their desktop parts (e.g., GV100) are a very powerful GPU that is used for training, the GPU here is optimized for inference. The most obvious change is that each Volta multiprocessor contains eight tensor cores, each of which can perform 64x FP16 MACs or 128x INT8 MACs per cycle. All of this yields a maximum 22.6 tera-operations (int8) per second.

Xavier implements a derivative of their {{nvidia|Volta|l=arch}} GPU with a set of finer changes to address the machine learning market, particularly improving inference performance over training. It has eight Volta stream multiprocessors along with their standard 128 KiB of L1 cache and a 512 KiB of shared L2. Compared to Parker, Nvidia claims this GPU has 2.1x the graphics performance. Whereas their desktop parts (e.g., GV100) are a very powerful GPU that is used for training, the GPU here is optimized for inference. The most obvious change is that each Volta multiprocessor contains eight tensor cores, each of which can perform 64x FP16 MACs or 128x INT8 MACs per cycle. All of this yields a maximum 22.6 tera-operations (int8) per second.

Xavier incorporates a set of accelerators designed to augment the functionality offered by the GPU and CPU in order to provide added flexibility and perhaps offer a way to implement some of the more common set of algorithms slightly more efficiently.

Xavier incorporates a set of accelerators designed to augment the functionality offered by the GPU and CPU in order to provide added flexibility and perhaps offer a way to implement some of the more common set of algorithms slightly more efficiently.

==== Programmable Vision Accelerator ====

==== Programmable Vision Accelerator ====

Xavier incorporates a Programmable Vision Accelerator (PVA) for processing computer vision. There are actually two exact instances of the PVA on-chip, each can be used in lock-step or independently and are capable of implementing some of the common filter loop and other detection algorithms (e.g. [[Harris corner]], [[fast Fourier transform|FFTs]]). For each of the PVAs, there is a {{armh|Cortex-R5|l=arch}} core along with two dedicated vector processing units, each with its own memory and DMA. The DMA on the PVA is designed to operate on tiles of memory. To that end, the DMA performs the address calculation and can perform prefetching while the processing pipes operate. This is 7-slot VLIW architecture made of 2 scalar slots, 2 vector slots, and 3 memory operations. The pipe is 256 bit wide (slightly wider because of the [[guard bits]] keeping the precision for the operation) and all types can operate at full throughput (32x8b, 16x16b, and 8x32b vector math). The pipe supports additional operations beyond vector such as custom logic for table lookup and hardware looping.

Xavier incorporates a Programmable Vision Accelerator (PVA) for processing computer vision. There are actually two exact instances of the PVA on-chip, each can be used in lock-step or independently and are capable of implementing some of the common filter loop and other detection algorithms (e.g. [[Harris corner]], [[fast Fourier transform|FFTs]]). For each of the PVAs, there is a {{armh|Cortex-R5|l=arch}} core along with two dedicated vector processing units, each with its own memory and DMA. The DMA on the PVA is designed to operate on tiles of memory. To that end, the DMA performs the address calculation and can perform prefetching while the processing pipes operate. This is 7-slot VLIW architecture made of 2 scalar slots, 2 vector slots, and 3 memory operations. The pipe is 256 bit wide (slightly wider because of the [[guard bits]] keeping the precision for the operation) and all types can operate at full throughput (32x8b, 16x16b, and 8x32b vector math). The pipe supports additional operations beyond vector such as custom logic for table lookup and hardware looping.