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Difference between revisions of "nvidia/microarchitectures/denver"
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(Start based on mpr 14 article Nvidia_Denverreprint.pdf)
 
(Denver is used in Tegra K1-64)
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{{nvidia title|denver}}
 
{{nvidia title|denver}}
 
{{microarchitecture
 
{{microarchitecture
| atype        = "CPU"
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| atype        = CPU
 
| name          = Denver
 
| name          = Denver
 
| designer      = Nvidia
 
| designer      = Nvidia
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| successor N link =  
 
| successor N link =  
 
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}}
''Denver'' is a CPU microarchitecture from [[Nvidia]], capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.
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'''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.
  
 
== Architecture ==
 
== Architecture ==
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== Products ==
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Denver is used in Tegra K1-64.
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== Die ==
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== All Denver Chips ==
 
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           This table is generated automatically from the data in the actual articles.

Revision as of 12:51, 16 June 2018

Edit Values
Denver µarch
General Info
Arch TypeCPU
DesignerNvidia
ManufacturerTSMC
Introduction2014
Process28 nm, 16 nm
Core Configs2, 4
Pipeline
OoOENo
Decode2-way
Instructions
ISAARMv8
Cache
L1I Cache128 KiB/core
4-way set associative
L1D Cache64 KiB/core
4-way set associative
L2 Cache2 MiB/core
16-way set associative

Denver is a CPU microarchitecture from Nvidia introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.

Architecture

Products

Denver is used in Tegra K1-64.

Die

All Denver Chips

 List of all Denver Chips
 Main processorIGP
ModelLaunchedDesignerFamilyProcessCoreCTL2$L3$FrequencyMax MemDesignerNameFrequency
Count: 0


References

  • NVIDIA’S FIRST CPU IS A WINNER. Denver Uses Dynamic Translation to Outperform Mobile Rivals. - Linley Gwennap (August 18, 2014)
codenameDenver +
core count2 + and 4 +
designerNvidia +
first launched2014 +
full page namenvidia/microarchitectures/denver +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameDenver +
process28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +