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Difference between revisions of "nvidia/microarchitectures/carmel"
(Created page with "{{nvidia title|Carmel|arch}} {{microarchitecture}}") |
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{{nvidia title|Carmel|arch}} | {{nvidia title|Carmel|arch}} | ||
| − | {{microarchitecture}} | + | {{microarchitecture |
| + | |atype=CPU | ||
| + | |name=Carmel | ||
| + | |designer=Nvidia | ||
| + | |manufacturer=TSMC | ||
| + | |introduction=January 7, 2018 | ||
| + | |process=12 nm | ||
| + | |cores=8 | ||
| + | |type=Superscalar | ||
| + | |oooe=Yes | ||
| + | |speculative=Yes | ||
| + | |renaming=Yes | ||
| + | |stages=10 | ||
| + | |isa=ARMv8 | ||
| + | |feature=RAS | ||
| + | |l2=2 MiB | ||
| + | |l2 per=cluster | ||
| + | |l3=4 MiB | ||
| + | |l3 per=complex | ||
| + | |predecessor=nvidia/microarchitectures/denver 2 | ||
| + | |predecessor link=Denver 2 | ||
| + | }} | ||
Revision as of 10:19, 30 August 2018
| Edit Values | |
| Carmel µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Nvidia |
| Manufacturer | TSMC |
| Introduction | January 7, 2018 |
| Process | 12 nm |
| Core Configs | 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 10 |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L2 Cache | 2 MiB/cluster |
| L3 Cache | 4 MiB/complex |
| Succession | |
Facts about "Carmel - Microarchitectures - Nvidia"
| codename | Carmel + |
| core count | 8 + |
| designer | Nvidia + |
| first launched | January 7, 2018 + |
| full page name | nvidia/microarchitectures/carmel + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Carmel + |
| pipeline stages | 10 + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |
