From WikiChip
Editing nvidia/microarchitectures/carmel

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 9: Line 9:
 
|cores=8
 
|cores=8
 
|type=Superscalar
 
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 
|isa=ARMv8
 
|isa=ARMv8
 
|feature=RAS
 
|feature=RAS
Line 18: Line 21:
 
|predecessor link=nvidia/microarchitectures/denver 2
 
|predecessor link=nvidia/microarchitectures/denver 2
 
}}
 
}}
−
'''Carmel''' is a the successor to {{\\|Denver 2}}, an [[ARM]] microarchitecture for [[Nvidia]]'s {{nvidia|Tegra}} series of [[SoCs]].
+
Carmel is a the successor to {{\\|Denver 2}}, an [[ARM]] microarchitecture for [[Nvidia]]'s {{nvidia|Tegra}} series of [[SoCs]].
−
 
 
−
== Process Technology ==
 
−
Carmel is integrated into chips fabricated on [[TSMC]] [[12 nm process]] (12FFN)
 
  
 
== Architecture ==
 
== Architecture ==
−
Nvidia disclosed very few details regarding Carmel. Carmel is a 10-wide superscalar with each core supporting dual execution mode.
+
Nvidia disclosed very few details regarding Carmel.
  
−
=== Key changes from {{\\|Denver 2}} ===
+
* [[12 nm]] (12FF)
−
* [[12 nm]] (12FFN)
+
* ARMv8.2 (Only AArch64)
−
* ARMv8.2
 
 
** ARM RAS standard support
 
** ARM RAS standard support
−
* Wider dispatch (10, up from 7)
+
* Eight-core cluster
 +
** 4x Core duplexes
 +
 
 +
== Overview ==
 +
Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
 
* Cache
 
* Cache
−
** Parity & ECC
 
 
** L1
 
** L1
 
** L2
 
** L2
Line 43: Line 45:
 
**** Shared by entire cluster
 
**** Shared by entire cluster
 
**** Exclusive
 
**** Exclusive
−
 
−
=== Block Diagram ===
 
−
==== CPU Complex ====
 
−
[[File:nvidia carmel complex diagram.svg|600px]]
 
−
 
−
== Overview ==
 
−
Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.
 
−
 
−
The cores consume 500-1,500 mW per core.
 
−
 
−
=== Performance claims ===
 
−
{| class="wikitable"
 
−
|-
 
−
! SPECint 2000 Rate !! SPECint 2006
 
−
|-
 
−
| 2700 || 21
 
−
|}
 
−
 
−
== Die ==
 
−
=== CPU Complex ===
 
−
* 8 cores
 
−
** 4 duplexes
 
−
** shared L3
 
−
* ~62.25 mm² die size area
 
−
 
−
:[[File:nvidia carmel complex.png|class=wikichip_ogimage|600px]]
 
−
 
−
 
−
:[[File:nvidia carmel complex (annotated).png|600px]]
 
−
 
−
=== CPU Duplex ===
 
−
* 2 cores
 
−
* ~11.4 mm² die size area
 
−
 
−
:[[File:nvidia carmel duplex.png|400px]]
 
−
 
−
 
−
:[[File:nvidia carmel duplex (annotated).png|400px]]
 
−
 
−
=== Core ===
 
−
* ~5.75 mm² die size area
 
−
 
−
:[[File:nvidia carmel core.png|200px]]
 
  
 
== Bibliography ==
 
== Bibliography ==
 
* IEEE Hot Chips 30 Symposium (HCS) 2018.
 
* IEEE Hot Chips 30 Symposium (HCS) 2018.

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/nvidia/microarchitectures/carmel"
Facts about "Carmel - Microarchitectures - Nvidia"
RDF feed
codenameCarmel +
core count8 +
designerNvidia +
first launchedJanuary 7, 2018 +
full page namenvidia/microarchitectures/carmel +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCarmel +
process12 nm (0.012 μm, 1.2e-5 mm) +