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{{main|nervana/microarchitectures/lake_crest|l1=Lake Crest µarch}} | {{main|nervana/microarchitectures/lake_crest|l1=Lake Crest µarch}} | ||
The first generation of NNPs were based on the {{nervana|Lake Crest|Lake Crest microarchitecture|l=arch}}. Manufactured on [[TSMC]]'s [[28 nm process]], those chips were never productized. Samples were used for customer feedback and the design mostly served as a software development vehicle for their follow-up design. | The first generation of NNPs were based on the {{nervana|Lake Crest|Lake Crest microarchitecture|l=arch}}. Manufactured on [[TSMC]]'s [[28 nm process]], those chips were never productized. Samples were used for customer feedback and the design mostly served as a software development vehicle for their follow-up design. | ||
− | === T-1000 | + | === T-1000 (Spring Crest) === |
[[File:nnp-l-1000 announcement.png|thumb|right|NNP T-1000]] | [[File:nnp-l-1000 announcement.png|thumb|right|NNP T-1000]] | ||
{{main|nervana/microarchitectures/spring_crest|l1=Spring Crest µarch}} | {{main|nervana/microarchitectures/spring_crest|l1=Spring Crest µarch}} |
Facts about "Neural Network Processors (NNP) - Intel Nervana"
designer | Intel + |
first announced | May 23, 2018 + |
first launched | 2019 + |
full page name | nervana/nnp + |
instance of | integrated circuit family + |
main designer | Intel + |
manufacturer | Intel + and TSMC + |
name | NNP + |
package | PCIe x16 Gen 3 Card +, OCP OAM + and M.2 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |
technology | CMOS + |