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|truth table = {{truth table/mux}} | |truth table = {{truth table/mux}} | ||
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− | A '''multiplexer''' ('''mux''') | + | A '''multiplexer''' ('''mux''') is a device that selects one of its inputs and connects it to its output. A set of inputs called select lines determine which input should be passed to the output. For a 2:1 (two-to-one) MUX, when sel is 0, q = a and when sel is 1, q = b. A multiplexer with 2<sup>N</sup> input lines requires ''N'' select lines. |
Multiplexers are useful in any application in which data must be chosen from multiple sources to a single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files. Additionally multiplexers have also found their way to various other circuits such as adders. | Multiplexers are useful in any application in which data must be chosen from multiple sources to a single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files. Additionally multiplexers have also found their way to various other circuits such as adders. | ||
− | == | + | == Enable == |
− | + | [[File:Mux enable.svg|150px|right]] | |
− | + | It's often desirable to add an enable input ''EN'' to a multiplexer. An enable input makes the multiplexer operate. When ''EN = 0'', the output is | |
+ | 0. When ''EN = 1'', the multiplexer performs its operation depending on the selection line. | ||
− | == | + | == Variations == |
− | + | Many different variations of multiplexers exist. | |
− | ''' | + | === 2:1 Mux === |
+ | A '''2:1 Mux''' is the simplest multiplexer that can be made. Its selection lines are made of a [[bit|single bit]]. A [[truth table]] is provided on the right. The logic function of a 2:1 Mux is: Q=(A ∧ <span style="text-decoration:overline;">S</span>) ∨ (B ∧ S) | ||
− | = | + | {| class="center" |
− | [[File: | + | |- |
− | + | | [[File:Mux 2 1 equivalence.svg|300px]] | |
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− | + | {| class="wikitable" | |
− | + | ! style="width:20em;" colspan="4" | 2:1 Mux | |
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− | {| class="wikitable" style=" | ||
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! Sel !! A !! B !! Q | ! Sel !! A !! B !! Q | ||
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− | | 0 || 0 || | + | | 0 || 0 || X || 0 |
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− | | 0 || 1 || | + | | 0 || 1 || X || 1 |
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− | | 1 || | + | | 1 || X || 0 || 0 |
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− | | 1 || | + | | 1 || X || 1 || 1 |
+ | |} | ||
|} | |} | ||
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{{clear}} | {{clear}} | ||
+ | Very fast, [[CMOS]]-based, 2:1 Mux devices can be built using two [[transmission gate]]s as shown below. Note that the implementation below is a nonrestoring multiplexer. | ||
− | + | [[File:Transmission gate 2 1 mux.png|300px|center]] | |
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{{clear}} | {{clear}} | ||
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=== 4:1 Mux === | === 4:1 Mux === | ||
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|+ 4:1 Mux | |+ 4:1 Mux | ||
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− | ! Sel< | + | ! Sel<0> !! Sel<1> !! I<0> !! I<1> !! I<2> !! I<3> !! Q |
|- | |- | ||
| 0 || 0 || 0 || X || X || X || 0 | | 0 || 0 || 0 || X || X || X || 0 | ||
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|- | |- | ||
| 1 || 0 || X || X || 1 || X || 1 | | 1 || 0 || X || X || 1 || X || 1 | ||
+ | |- | ||
+ | | 1 || 1 || X || X || X || 1 || 1 | ||
|- | |- | ||
| 1 || 1 || X || X || X || 0 || 0 | | 1 || 1 || X || X || X || 0 || 0 | ||
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|} | |} | ||
A '''4:1''' Multiplexer is a common multiplexer that takes selects one input among 4 and connects it to its output based on a 2-bit select line. There are many way to construct a 4:1 Mux, one possibility is using 2:1 Mux as shown below: | A '''4:1''' Multiplexer is a common multiplexer that takes selects one input among 4 and connects it to its output based on a 2-bit select line. There are many way to construct a 4:1 Mux, one possibility is using 2:1 Mux as shown below: | ||
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Alternatively, a 4:1 Mux can be built out of basic gates. Its function is shown below: | Alternatively, a 4:1 Mux can be built out of basic gates. Its function is shown below: | ||
− | Q = <math>(A \land \overline S_0 \land \overline S_1) \lor (B \land S_0 \land | + | Q = <math>(A \land \overline S_0 \land \overline S_1) \lor (B \land \overline S_0 \land S_1) \lor (C \land S_0 \land \overline S_1) \lor (D \land S_0 \land S_1)</math> |
Where A, B, C, and D are the four inputs. Q is the output. | Where A, B, C, and D are the four inputs. Q is the output. | ||
− | === | + | === Larger Multiplexers === |
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Multiplexers generally only come in a few common sizes. Even in [[ASIC]] design, arbitrary sized multiplexers are not always offered. Large multiplexers can always be built from a collection of smaller ones. Consider a [[register file]] with 32 registers where we only want to select a single register at any given time. Such multiplexer can be design from four 8:1 Mux. | Multiplexers generally only come in a few common sizes. Even in [[ASIC]] design, arbitrary sized multiplexers are not always offered. Large multiplexers can always be built from a collection of smaller ones. Consider a [[register file]] with 32 registers where we only want to select a single register at any given time. Such multiplexer can be design from four 8:1 Mux. | ||
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==== 74151 - 8:1 Mux ==== | ==== 74151 - 8:1 Mux ==== | ||
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[[File:74151.svg|left|thumb|300px|74151 IC 8:1 MUX]] | [[File:74151.svg|left|thumb|300px|74151 IC 8:1 MUX]] | ||
{{clear}} | {{clear}} | ||
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+ | == Tri-State Outputs == | ||
+ | Some commercial multiplexers have tri-state outputs. When the EN input is LOW, instead of the output being forced into 0, it gets forced into a Hi-Z state. | ||
== See also == | == See also == | ||
* [[choose function]] | * [[choose function]] | ||
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[[Category:Logic gates]] | [[Category:Logic gates]] |