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SHAVE v2.0 - Microarchitectures - Intel Movidius
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SHAVE v2.0 µarch
General Info
Arch TypeAccelerator
DesignerMovidius
ManufacturerTSMC
Introduction2011
Pipeline
TypeVLIW

Streaming Hybrid Architecture Vector Engine v2.0 (SHAVE v2.0) is an accelerator microarchitecture designed by Movidius for their vision processors. SHAVE is incorporated into Movidius Myriad family of vision processors.

Architecture

Instruction Set

SHAVE supports a mixture of many different types of instructions belonging to a number of different classes of architectures.

  • RISC style
    • Instruction predication
    • Large set of integer operations
    • C-compiler support
  • VLIW style
    • Parallel functional units controlled by VLIW instructions
    • 8/16/32-bit x 1-4 SIMD int
  • DSP style
    • Zero overhead looping
    • Modulo addressing
    • Transparent DMA modes
    • FFT, Viterbi, etc..
    • Parallel comparisons
  • GPU style
    • Streaming operations
    • 16/32-bit FP operations
    • Texture management unit

Block Diagram

Individual Core

shave v2 block diagram.svg

codenameSHAVE v2.0 +
designerMovidius +
first launched2011 +
full page namemovidius/microarchitectures/shave v2.0 +
instance ofmicroarchitecture +
manufacturerTSMC +
nameSHAVE v2.0 +