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Difference between revisions of "movidius/microarchitectures/shave v2.0"
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(Instruction Set)
(Architecture)
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* Hybrid [[RISC]]-[[DSP]]-[[GPU]] [[VLIW]] architecture
 
* Hybrid [[RISC]]-[[DSP]]-[[GPU]] [[VLIW]] architecture
 
* 20 GFLOPS computational power
 
* 20 GFLOPS computational power
 +
** 180 MHz
 
** At 300 mW
 
** At 300 mW
 
* [[Predicated execution]]
 
* [[Predicated execution]]

Revision as of 16:34, 11 March 2018

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SHAVE v2.0 µarch
General Info
Arch TypeAccelerator
DesignerMovidius
ManufacturerTSMC
Introduction2011
Pipeline
TypeVLIW

Streaming Hybrid Architecture Vector Engine v2.0 (SHAVE v2.0) is an accelerator microarchitecture designed by Movidius for their vision processors. SHAVE is incorporated into Movidius Myriad family of vision processors.

History

The original SHAVE architecture was designed primarily for the acceleration of game physics. Low demand for expensive physics acceleration in smartphones has forced to re-focused on image and vision processing. Their architecture was versatile enough that it allowed for fairly simple modification to target machine vision processing.

Process Technology

Main article: 65 nm lithography process

This microarchitecture was designed for TSMC's 65 nm process.

Architecture

Instruction Set

SHAVE supports a mixture of many different types of instructions belonging to a number of different classes of architectures.

  • RISC style
    • Instruction predication
    • Large set of integer operations
  • VLIW style
    • Parallel functional units controlled by VLIW instructions
    • 8/16/32-bit x 1-4 SIMD int
  • DSP style
    • Zero overhead looping
    • Modulo addressing
    • Transparent DMA modes
    • FFT, Viterbi, etc..
    • Parallel comparisons
  • GPU style
    • Streaming operations
    • 16/32-bit FP operations
    • Texture management unit

Block Diagram

Entire SoC

shave v2 soc block.svg

Individual Core

shave v2 block diagram.svg

codenameSHAVE v2.0 +
designerMovidius +
first launched2011 +
full page namemovidius/microarchitectures/shave v2.0 +
instance ofmicroarchitecture +
manufacturerTSMC +
nameSHAVE v2.0 +