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Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. | Movidius packaged those chips in an 8x8 mm [[BGA]] package with 225 [[solder ball|balls]]. The die is then bumped on top of a custom [[FR-4 substrate]]. The SDRAM is then [[wire bond|wire bond]] on top of the Myriad die. | ||
− | :[[File:myriad package diagram.svg| | + | :[[File:myriad package diagram.svg|500px]] |
== Floorplan == | == Floorplan == |
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |