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Difference between revisions of "mediatek/helio/mt6757"
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{{mediatek title|Helio P20 (MT6757)}}
 
{{mediatek title|Helio P20 (MT6757)}}
 
{{mpu
 
{{mpu
−
| future             = Yes
+
|future=Yes
−
| name               = MediaTek Helio P20
+
|name=MediaTek Helio P20
−
| no image            = yes
+
|designer=MediaTek
−
| image              =
+
|designer 2=ARM Holdings
−
| image size          =
+
|manufacturer=TSMC
−
| caption            =
+
|model number=Helio P20
−
| designer           = MediaTek
+
|part number=MT6757
−
| designer 2         = ARM Holdings
+
|part number 2=MTK6757
−
| manufacturer       = TSMC
+
|market=Mobile
−
| model number       = Helio P20
+
|market 2=Embedded
−
| part number         = MT6757
+
|first announced=September 22, 2016
−
| part number 2       = MTK6757
+
|first launched=2017
−
| market             = Mobile
+
|family=Helio
−
| market 2           = Embedded
+
|series=Helio P
−
| first announced     = September 22, 2016
+
|frequency=2,300 MHz
−
| first launched     = 2017
+
|bus type=AMBA 4 AXI
−
| last order          =
+
|isa=ARMv8
−
| last shipment      =
+
|isa family=ARM
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| release price      =
+
|microarch=Cortex-A53
−
 
+
|core name=Cortex-A53
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| family             = Helio
+
|process=16 nm
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| series             = Helio P
+
|technology=CMOS
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| locked              =
+
|word size=64 bit
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| frequency           = 2,300 MHz
+
|core count=8
−
| frequency 2        =
+
|thread count=8
−
| bus type           = AMBA 4 AXI
+
|max cpus=1
−
| bus speed          =
+
|max memory=6 GiB
−
| bus rate            =  
 
−
| bus links          =
 
−
| clock multiplier    =
 
−
 
 
−
| isa family         = ARM
 
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| isa                = ARMv8
 
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| microarch           = Cortex-A53
 
−
| platform            =
 
−
| chipset            =
 
−
| core name           = Cortex-A53
 
−
| core family        =
 
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| core model          =
 
−
| core stepping      =
 
−
| process             = 16 nm
 
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area            = <!-- XX mm² -->
 
−
| die width          =
 
−
| die length          =
 
−
| word size           = 64 bit
 
−
| core count         = 8
 
−
| thread count       = 8
 
−
| max cpus           = 1
 
−
| max memory         = 6 GiB
 
−
 
 
−
| electrical          =
 
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| power              =
 
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| v core              =
 
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| v core tolerance    =
 
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| v io                =
 
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| v io 2              =
 
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| v io 3              =
 
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| sdp                =
 
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| tdp                =
 
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| tdp typical        =
 
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| ctdp down          =
 
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| ctdp down frequency =
 
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| ctdp up            =
 
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| ctdp up frequency  =
 
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| temp min            =
 
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| temp max            =
 
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| tjunc min          =
 
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| tjunc max          =
 
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| tcase min          =
 
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| tcase max          =
 
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| tstorage min        = <!-- °C -->
 
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| tstorage max        =
 
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| tambient min        =
 
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| tambient max        =
 
−
 
 
−
| packaging          =
 
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| package 0          =
 
−
| package 0 type      =
 
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| package 0 pins      =
 
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| package 0 pitch    =
 
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| package 0 width    =
 
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| package 0 length    =
 
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| package 0 height    =
 
 
}}
 
}}
 
'''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports  up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
 
'''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and set to be launched in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports  up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.

Revision as of 17:08, 12 July 2017

Template:mpu Helio P20 (MT6757) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and set to be launched in 2017. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 16 nm process, operates at up to 2.3 GHz and supports up to 6 GiB of dual-channel LPDDR4X-3200 memory. This chip incorporates the Mali-T880 IGP operating at 900 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3200
Supports ECCNo
Max Mem6 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth23.84 GiB/s
24,412.16 MiB/s
25.598 GB/s
25,598.005 MB/s
0.0233 TiB/s
0.0256 TB/s
Bandwidth
Single 11.92 GiB/s
Double 23.84 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-T880
DesignerARM Holdings
Execution Units2Max Displays2
Frequency900 MHz
0.9 GHz
900,000 KHz
OutputDSI
Max Resolution
DSI1920x1080
Standards
Direct3D11.2
OpenGL3.2
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
4G
LTE Advanced
E-UTRANYes
UE Cat6

Image

New text document.svg This section is empty; you can help add the missing info by editing this page.

Video

New text document.svg This section is empty; you can help add the missing info by editing this page.

Audio

New text document.svg This section is empty; you can help add the missing info by editing this page.

Utilizing devices

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6757&oldid=54640"
Facts about "Helio P20 (MT6757) - MediaTek"
RDF feed
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
integrated gpuMali-T880 +
integrated gpu base frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units2 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels2 +
supported memory typeLPDDR4X-3200 +
user equipment category6 +