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Difference between revisions of "mediatek/helio/mt6757"
(Created page with "{{mediatek title|Helio P20 (MT6757)}} {{mpu | future = Yes | name = MediaTek Helio P20 | no image = yes | image = | image...") |
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| last shipment = | | last shipment = | ||
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| + | |||
| + | | family = Helio | ||
| + | | series = Helio P | ||
| + | | locked = | ||
| + | | frequency = 2,300 MHz | ||
| + | | frequency 2 = | ||
| + | | bus type = AMBA 4 AXI | ||
| + | | bus speed = | ||
| + | | bus rate = | ||
| + | | bus links = | ||
| + | | clock multiplier = | ||
| + | |||
| + | | isa family = ARM | ||
| + | | isa = ARMv8 | ||
| + | | microarch = Cortex-A53 | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = Cortex-A53 | ||
| + | | core family = | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | process = 16 nm | ||
| + | | transistors = | ||
| + | | technology = CMOS | ||
| + | | die area = <!-- XX mm² --> | ||
| + | | die width = | ||
| + | | die length = | ||
| + | | word size = 64 bit | ||
| + | | core count = 8 | ||
| + | | thread count = 8 | ||
| + | | max cpus = 1 | ||
| + | | max memory = 4 GiB | ||
| + | |||
| + | | electrical = | ||
| + | | power = | ||
| + | | v core = | ||
| + | | v core tolerance = | ||
| + | | v io = | ||
| + | | v io 2 = | ||
| + | | v io 3 = | ||
| + | | sdp = | ||
| + | | tdp = | ||
| + | | tdp typical = | ||
| + | | ctdp down = | ||
| + | | ctdp down frequency = | ||
| + | | ctdp up = | ||
| + | | ctdp up frequency = | ||
| + | | temp min = | ||
| + | | temp max = | ||
| + | | tjunc min = | ||
| + | | tjunc max = | ||
| + | | tcase min = | ||
| + | | tcase max = | ||
| + | | tstorage min = <!-- °C --> | ||
| + | | tstorage max = | ||
| + | | tambient min = | ||
| + | | tambient max = | ||
| + | |||
| + | | packaging = | ||
| + | | package 0 = | ||
| + | | package 0 type = | ||
| + | | package 0 pins = | ||
| + | | package 0 pitch = | ||
| + | | package 0 width = | ||
| + | | package 0 length = | ||
| + | | package 0 height = | ||
}} | }} | ||
| + | '''Helio P20''' ('''MT6757''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in [[2017]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[16 nm process]], operates at up to 2.3 GHz and supports double-channel LPDDR4-1600. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 900 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6. | ||
Revision as of 21:55, 5 December 2016
Template:mpu Helio P20 (MT6757) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in 2017. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 16 nm process, operates at up to 2.3 GHz and supports double-channel LPDDR4-1600. This chip incorporates the Mali-T880 IGP operating at 900 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.
