Difference between revisions of "mediatek/helio/mt6755t"

	Edit Values
	Helio P15
	General Info
Designer	MediaTek,; ARM Holdings
Manufacturer	TSMC
Model Number	P15
Part Number	MT6755T
Market	Mobile, Embedded
Introduction	October 17, 2016 (announced); April, 2017 (launched)
	General Specs
Family	Helio
Series	Helio P
Frequency	2,200 MHz, 1,200 MHz
Bus type	AMBA 4 AXI
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A53
Core Name	Cortex-A53
Process	28 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	8
Max Memory	4 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
Vcore	1 V
VI/O	1.8 V, 2.8 V, 3.3 V
OP Temperature	-20 °C – 80 °C
Tjunction	– 125 °C
Tstorage	0 °C – 125 °C

Latest revision as of 23:18, 3 November 2019

Helio P15 (MT6755T) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2016. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2.2 GHz and supports up to 4 GiB of single-channel LPDDR3-1866 memory. This chip incorporates the Mali-T880 IGP operating at 800 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 6.

This processor is made of two independent clusters of Cortex-A53 with four cores each linked together via a CCI-400. The two clusters have a maximum operating frequency of 2.2 GHz and 1.2 GHz respectively.

The Helio P15 is identical to the Helio P10 with higher clock speeds for both the GPU and CPU.

Cache[edit]

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	2-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	4-way set associative

L2$

2 MiB

2,048 KiB
2,097,152 B
0.00195 GiB

		2x1 MiB	16-way set associative

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	LPDDR3-1866
Supports ECC	No
Max Mem	4 GiB
Controllers	1
Channels	1
Width	32 bit
Max Bandwidth	6.95 GiB/s 7,116.8 MiB/s 7.463 GB/s 7,462.506 MB/s 0.00679 TiB/s 0.00746 TB/s
Bandwidth	Single 6.95 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

USB

Revision	2.0, 3.0
Ports	8

UART

GP I/O	Yes

Graphics[edit]

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

Mali-T860

Designer

ARM Holdings

Execution Units

2

Frequency

800 MHz

0.8 GHz
800,000 KHz

Output

DSI

Max Resolution

DSI	1920x1080

Standards

Direct3D	11.2
OpenGL	3.2
OpenCL	1.2
OpenGL ES	3.2
OpenVG	1.1
Vulkan	1.0

Wireless[edit]

Wireless Communications

Wi-Fi

WiFi

802.11n	Yes

Cellular

2G

CSD		Yes
GSM		Yes
GPRS		Yes
EDGE		Yes

3G

UMTS

TD-SCDMA	Yes
DC-HSDPA	Yes
HSUPA	Yes

4G

LTE Advanced

E-UTRAN	Yes
UE Cat	6

Image[edit]

Integrated image signal processor supports 21 MP
Supports image stabilization
Supports video stabilization
Supports noise reduction
Supports lens shading correction
Supports AE/AWB/AF
Supports edge enhancement
Supports face detection and visual tracking
Hardware JPEG encoder

Video[edit]

HEVC decoder 4k2k @ 30fps
H.264 decoder (30fps/40Mbps)
Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps)
VP8 / VC-1 decoders
MPEG-4 / H.263 / H.264 / HEVC encoders

Audio[edit]

Audio content sampling rates 8kHz to 192kHz
Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
I2S, PCM
Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
7.1 channel MHL output

Utilizing devices[edit]

Motorola Moto M

This list is incomplete; you can help by expanding it.

@@ Line 1: / Line 1: @@
-{{mediatek title|Helio P15}}
+{{mediatek title|Helio P15 (MT6755T)}}
-{{mpu
+{{chip
-| future              = Yes
+|name=Helio P15
-| name                = MediaTek Helio P15
+|no image=Yes
-| no image            = yes
+|designer=MediaTek
-| image               =
+|designer 2=ARM Holdings
-| image size          =
+|manufacturer=TSMC
-| caption             =
+|model number=P15
-| designer            = MediaTek
+|part number=MT6755T
-| designer 2          = ARM Holdings
+|market=Mobile
-| manufacturer        = TSMC
+|market 2=Embedded
-| model number        = Helio P15
+|first announced=October 17, 2016
-| part number         = MT6755T?
+|first launched=April, 2017
-| part number 2       = MTK6755T?
+|family=Helio
-| market              = Mobile
+|series=Helio P
-| market 2            = Embedded
+|frequency=2,200 MHz
-| first announced     = October 17, 2016
+|frequency 2=1,200 MHz
-| first launched      =
+|bus type=AMBA 4 AXI
-| last order          =
+|isa=ARMv8
-| last shipment       =
+|isa family=ARM
-| release price       =
+|microarch=Cortex-A53
+|core name=Cortex-A53
-| family              = Helio
+|process=28 nm
-| series              = Helio P
+|technology=CMOS
-| locked              =
+|word size=64 bit
-| frequency           = 2,200 MHz
+|core count=8
-| frequency 2         = 1,200 MHz
+|thread count=8
-| bus type            = AMBA 4 AXI
+|max cpus=1
-| bus speed           =
+|max memory=4 GiB
-| bus rate            =
+|v core=1 V
-| bus links           =
+|v io=1.8 V
-| clock multiplier    =
+|v io 2=2.8 V
+|v io 3=3.3 V
-| isa family          = ARM
+|temp min=-20 °C
-| isa                 = ARMv8
+|temp max=80 °C
-| microarch           = Cortex-A53
+|tjunc max=125 °C
-| platform            =
+|tstorage min=0 °C
-| chipset             =
+|tstorage max=125 °C
-| core name           = Cortex-A53
-| core family         =
-| core model          =
-| core stepping       =
-| process             = 28 nm
-| transistors         =
-| technology          = CMOS
-| die area            = <!-- XX mm² -->
-| die width           =
-| die length          =
-| word size           = 64 bit
-| core count          = 8
-| thread count        = 8
-| max cpus            = 1
-| max memory          = 4 GiB
-| electrical          = Yes
-| power               =
-| v core              = 1 V
-| v core tolerance    =
-| v io                = 1.8 V
-| v io 2              = 2.8 V
-| v io 3              = 3.3 V
-| sdp                 =
-| tdp                 =
-| tdp typical         =
-| ctdp down           =
-| ctdp down frequency =
-| ctdp up             =
-| ctdp up frequency   =
-| temp min            = -20 °C
-| temp max            = 80 °C
-| tjunc min           =
-| tjunc max           = 125 °C
-| tcase min           =
-| tcase max           =
-| tstorage min        = 0 °C
-| tstorage max        = 125 °C
-| tambient min        =
-| tambient max        =
-| packaging           =
-| package 0           =
-| package 0 type      =
-| package 0 pins      =
-| package 0 pitch     =
-| package 0 width     =
-| package 0 length    =
-| package 0 height    =
 }}
-'''Helio P15''' ('''MT6755T'''?) is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[28 nm process]], operates at up to 2.2 GHz and supports single-channel LPDDR3-933. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 800  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
+'''Helio P15''' ('''MT6755T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2016]]. This SoC, which incorporates eight {{armh|Cortex-A53|l=arch}} cores and is manufactured on [[TSMC]]'s [[28 nm process]], operates at up to 2.2 GHz and supports up to 4 GiB of single-channel LPDDR3-1866 memory. This chip incorporates the {{imgtec|Mali-T880}} [[IGP]] operating at 800  MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 6.
 This processor is made of two independent clusters of {{armh|Cortex-A53|l=arch}} with four cores each linked together via a {{armh|CCI-400}}. The two clusters have a maximum operating frequency of 2.2 GHz and 1.2 GHz respectively.
 The Helio P15 is identical to the {{\\|Helio P10}} with higher clock speeds for both the GPU and CPU.
 == Cache ==
 {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
@@ Line 109: / Line 61: @@
 == Memory controller ==
 {{memory controller
-|type=LPDDR3-933
+|type=LPDDR3-1866
 |ecc=No
 |max mem=4 GiB
 |controllers=1
 |channels=1
+|width=32 bit
 |max bandwidth=6.95 GiB/s
 |bandwidth schan=6.95 GiB/s
@@ Line 207: / Line 160: @@
 == Utilizing devices ==
-{{empty section}}
+* [[used by::Motorola Moto M]]
-<!--
-* [[used by::xxxxxxxxxxxxxxx]]
-* [[used by::xxxxxxxxxxxxxxx]]
--->
 {{expand list}}

base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) + and 1,200 MHz (1.2 GHz, 1,200,000 kHz) +
bus type	AMBA 4 AXI +
core count	8 +
core name	Cortex-A53 +
core voltage	1 V (10 dV, 100 cV, 1,000 mV) +
designer	MediaTek + and ARM Holdings +
family	Helio +
first announced	October 17, 2016 +
first launched	April 2017 +
full page name	mediatek/helio/mt6755t +
has 2g support	true +
has 3g support	true +
has 4g support	true +
has csd support	true +
has dc-hsdpa support	true +
has e-utran support	true +
has ecc memory support	false +
has edge support	true +
has gprs support	true +
has gsm support	true +
has hsupa support	true +
has lte advanced support	true +
has td-scdma support	true +
has umts support	true +
instance of	microprocessor +
integrated gpu	Mali-T860 +
integrated gpu base frequency	800 MHz (0.8 GHz, 800,000 KHz) +
integrated gpu designer	ARM Holdings +
integrated gpu execution units	2 +
io voltage	1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.8 V (28 dV, 280 cV, 2,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isa	ARMv8 +
isa family	ARM +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	4-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	2-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	April 2017 +
manufacturer	TSMC +
market segment	Mobile + and Embedded +
max cpu count	1 +
max junction temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
max memory	4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth	6.95 GiB/s (7,116.8 MiB/s, 7.463 GB/s, 7,462.506 MB/s, 0.00679 TiB/s, 0.00746 TB/s) +
max memory channels	1 +
max operating temperature	80 °C +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Cortex-A53 +
min operating temperature	-20 °C +
min storage temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	P15 +
name	Helio P15 +
part number	MT6755T +
process	28 nm (0.028 μm, 2.8e-5 mm) +
series	Helio P +
smp max ways	1 +
supported memory type	LPDDR3-1866 +
technology	CMOS +
thread count	8 +
used by	Motorola Moto M +
user equipment category	6 +
word size	64 bit (8 octets, 16 nibbles) +

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