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Difference between revisions of "majority gate"

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The '''majority gate''' ('''MAJ gate''') is a [[logic gate]] that implements the [[majority function]] - a device that outputs a [[HIGH]] when the majority of its inputs are HIGH, otherwise it outputs a [[LOW]].
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The '''majority gate''' ('''MAJ gate''') is a [[logic gate]] that implements the [[majority function]] - a device that outputs a [[HIGH]] when the majority of its inputs are HIGH, otherwise it outputs a [[LOW]].
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== MAJ3 ==
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<span style="display:inline-block;float: right; margin: 5px;">[[File:MAJ3 gate.svg|250px]]</span>
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A 3-input MAJ gate (MAJ3) can be implemented as <math>(a \land b) \lor (a \land c) \lor (b \land c)</math>. However the naive implementation will result in up to 30 transistors. Since <math>\text{MAJ}(a, b, c) = \overline{\overline{\text{MAJ}(a, b, c)}}</math>, we can define <math>\text{MAJ}(a, b, c) = \overline{\overline{(a \land b) \lor (a \land c) \lor (b \land c)}}</math> and that can be implemented using a single [[AOI|AOI222]] which is defined as <math>\text{AOI222}(a, b, c, d, e, f) = \overline{(a \land b) \lor (c \land d) \lor (e \land f)}</math> - i.e. <math>\text{MAJ}(a, b, c) = \overline{AOI222(a, b, c, a, b, c)}</math>.

Revision as of 05:35, 25 November 2015

MAJ Gate
Typical Symbol
maj gate.svg
Functional
maj gate functional.gif
Truth Table
3-input Majority Gate
Inputs Outputs
A B C Q
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Other Gates
Buffer TriBuffer NOT
AND OR XOR
NAND NOR XNOR
Trans AOI OAI
MAJ INH IMPLY
NIMPLY
Other Components
Plexers
MUX DEMUX Encoder
Decoder Pri-Encoder
ALU
Adder Subtractor Multiplier
Divider Shifter Rotator
MAC Comparator Negator
Memory
D latch D flip-flop SR latch
JK flip-flop T flip-flop Register
Register file SRAM Counter
ROM CAM DRAM
I/O
Shift register SIPO PISO
ADC DAC

The majority gate (MAJ gate) is a logic gate that implements the majority function - a device that outputs a HIGH when the majority of its inputs are HIGH, otherwise it outputs a LOW.

MAJ3

MAJ3 gate.svg A 3-input MAJ gate (MAJ3) can be implemented as Equation left-parenthesis a logical-and b right-parenthesis logical-or left-parenthesis a logical-and c right-parenthesis logical-or left-parenthesis b logical-and c right-parenthesis . However the naive implementation will result in up to 30 transistors. Since Equation MAJ left-parenthesis a comma b comma c right-parenthesis equals ModifyingAbove Above ModifyingAbove MAJ left-parenthesis a comma b comma c right-parenthesis With bar With bar , we can define Equation MAJ left-parenthesis a comma b comma c right-parenthesis equals ModifyingAbove Above ModifyingAbove left-parenthesis a logical-and b right-parenthesis logical-or left-parenthesis a logical-and c right-parenthesis logical-or left-parenthesis b logical-and c right-parenthesis With bar With bar and that can be implemented using a single AOI222 which is defined as Equation AOI 222 left-parenthesis a comma b comma c comma d comma e comma f right-parenthesis equals ModifyingAbove left-parenthesis a logical-and b right-parenthesis logical-or left-parenthesis c logical-and d right-parenthesis logical-or left-parenthesis e logical-and f right-parenthesis With bar - i.e. Equation MAJ left-parenthesis a comma b comma c right-parenthesis equals ModifyingAbove upper A upper O upper I Baseline 222 left-parenthesis a comma b comma c comma a comma b comma c right-parenthesis With bar .