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Difference between revisions of "list of microarchitectures"
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| count = 4 | | count = 4 | ||
| | | | ||
| − | * {{amd| | + | * {{amd|K5|l=arch}} |
| − | * {{amd| | + | * {{amd|K6|l=arch}} |
| − | * {{amd| | + | * {{amd|K6-2|l=arch}} |
| − | * {{amd| | + | * {{amd|K6-III|l=arch}} |
| − | * {{amd| | + | * {{amd|K7|l=arch}} |
| − | * {{amd| | + | * {{amd|K8|l=arch}} (Hammer) |
| − | * {{amd| | + | * {{amd|K9|l=arch}} |
| − | * {{amd| | + | * {{amd|K10|l=arch}} |
| − | * {{amd| | + | * {{amd|Bulldozer|l=arch}} |
| − | * {{amd| | + | * {{amd|Piledriver|l=arch}} |
| − | * {{amd| | + | * {{amd|Steamroller|l=arch}} |
| − | * {{amd| | + | * {{amd|Excavator|l=arch}} |
| − | * {{amd| | + | * {{amd|Zen|l=arch}} |
| − | * {{amd| | + | * {{amd|Zen refresh| l=arch}} |
| − | * {{amd| | + | * {{amd|Zen 2|l=arch}} |
| + | * {{amd|Zen 3|l=arch}} | ||
}} | }} | ||
'''ULV:''' | '''ULV:''' | ||
{{collist | {{collist | ||
| count = 2 | | count = 2 | ||
| − | |||
| | | | ||
* {{amd|Bobcat}} | * {{amd|Bobcat}} | ||
* {{amd|Jaguar}} | * {{amd|Jaguar}} | ||
| + | * {{amd|Enhanced Jaguar|l=arch}} | ||
* {{amd|Puma}} | * {{amd|Puma}} | ||
}} | }} | ||
| Line 35: | Line 36: | ||
{{collist | {{collist | ||
| count = 2 | | count = 2 | ||
| − | |||
| | | | ||
| − | * {{amd| | + | * {{amd|Southern Islands|l=arch}} |
| − | * {{amd| | + | * {{amd|Sea Islands|l=arch}} |
| − | * {{amd| | + | * {{amd|Volcanic Islands|l=arch}} |
| − | * {{amd| | + | * {{amd|Arctic Islands|l=arch}} |
| − | * {{amd| | + | * {{amd|Vega|l=arch}} |
| − | * {{amd| | + | * {{amd|Navi|l=arch}} |
}} | }} | ||
| Line 100: | Line 100: | ||
* {{armh|Cortex-R7|l=arch}} | * {{armh|Cortex-R7|l=arch}} | ||
* {{armh|Cortex-R8|l=arch}} | * {{armh|Cortex-R8|l=arch}} | ||
| + | * {{armh|Neoverse N1|l=arch}} | ||
* {{armh|SecurCore SC000|l=arch}} | * {{armh|SecurCore SC000|l=arch}} | ||
* {{armh|SecurCore SC100|l=arch}} | * {{armh|SecurCore SC100|l=arch}} | ||
* {{armh|SecurCore SC300|l=arch}} | * {{armh|SecurCore SC300|l=arch}} | ||
| + | |||
}} | }} | ||
| − | |||
== [[Cavium]]== | == [[Cavium]]== | ||
| Line 162: | Line 163: | ||
* {{intel|P6|l=arch}} | * {{intel|P6|l=arch}} | ||
* {{intel|NetBurst|l=arch}} | * {{intel|NetBurst|l=arch}} | ||
| + | * {{intel|Enhanced NetBurst|l=arch}} | ||
* {{intel|Core|l=arch}} | * {{intel|Core|l=arch}} | ||
* {{intel|Penryn|l=arch}} | * {{intel|Penryn|l=arch}} | ||
| Line 170: | Line 172: | ||
* {{intel|Haswell|l=arch}} | * {{intel|Haswell|l=arch}} | ||
* {{intel|Broadwell|l=arch}} | * {{intel|Broadwell|l=arch}} | ||
| − | * {{intel|Skylake| | + | * Skylake ({{intel|Skylake|client}}, {{intel|Skylake (server)|server}}) |
* {{intel|Kaby Lake|l=arch}} | * {{intel|Kaby Lake|l=arch}} | ||
* {{intel|Coffee Lake|l=arch}} | * {{intel|Coffee Lake|l=arch}} | ||
| + | * {{intel|Cascade Lake|l=arch}} | ||
* {{intel|Cannonlake|l=arch}} ("Skymont") | * {{intel|Cannonlake|l=arch}} ("Skymont") | ||
| − | * {{intel| | + | * {{intel|Ice Lake|l=arch}} |
* {{intel|Tigerlake|l=arch}} | * {{intel|Tigerlake|l=arch}} | ||
| + | * {{intel|Sapphire Rapids|l=arch}} | ||
}} | }} | ||
'''ULP ([[x86]]):''' | '''ULP ([[x86]]):''' | ||
| Line 186: | Line 190: | ||
* {{intel|Airmont|l=arch}} | * {{intel|Airmont|l=arch}} | ||
* {{intel|Goldmont|l=arch}} | * {{intel|Goldmont|l=arch}} | ||
| + | * {{intel|Goldmont Plus|l=arch}} | ||
| + | }} | ||
| + | '''MCU:''' | ||
| + | {{collist | ||
| + | | count = 1 | ||
| + | | | ||
| + | * {{intel|Lakemont|l=arch}} | ||
}} | }} | ||
'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
| Line 217: | Line 228: | ||
* {{intel|Kittson|l=arch}} | * {{intel|Kittson|l=arch}} | ||
}} | }} | ||
| − | ''' | + | '''{{intel|MIC Architectures}}:''' |
{{collist | {{collist | ||
| − | | count = | + | | count = 3 |
| | | | ||
| − | * {{intel|Larrabee}} | + | * {{intel|Larrabee|l=arch}} |
| + | * {{intel|Knights Ferry|l=arch}} | ||
| + | * {{intel|Knights Corner|l=arch}} | ||
| + | * {{intel|Knights Landing|l=arch}} | ||
| + | * {{intel|Knights Hill|l=arch}} | ||
| + | * {{intel|Knights Mill|l=arch}} | ||
}} | }} | ||
'''GPU:''' | '''GPU:''' | ||
| Line 244: | Line 260: | ||
* {{intel|Gen11|l=arch}} | * {{intel|Gen11|l=arch}} | ||
}} | }} | ||
| − | |||
== [[Loongson]] == | == [[Loongson]] == | ||
| Line 286: | Line 301: | ||
* {{qualcomm|Adreno|l=arch}} | * {{qualcomm|Adreno|l=arch}} | ||
* {{qualcomm|Venus|l=arch}} | * {{qualcomm|Venus|l=arch}} | ||
| + | * {{qualcomm|Kryo|l=arch}} | ||
}} | }} | ||
| Line 302: | Line 318: | ||
== See also == | == See also == | ||
* [[Microarchitecture]] | * [[Microarchitecture]] | ||
| + | |||
| + | [[Category:microprocessors]] | ||
Latest revision as of 11:36, 4 June 2020
Below is a list of microarchitectures organized by company, alphabetized.
Contents
AMD[edit]
Mainstream:
ULV:
GPU:
Apple[edit]
ARM Holdings[edit]
- ARM10E
- ARM11
- ARM1
- ARM250
- ARM2
- ARM3
- ARM6
- ARM7EJ
- ARM7
- ARM7TDMI
- ARM9E
- ARM9TDMI
- Cortex-A12
- Cortex-A15
- Cortex-A17
- Cortex-A32
- Cortex-A35
- Cortex-A53
- Cortex-A55
- Cortex-A57
- Cortex-A5
- Cortex-A72
- Cortex-A73
- Cortex-A75
- Cortex-A7
- Cortex-A8
- Cortex-A9
- Cortex-M0
- Cortex-M0+
- Cortex-M1
- Cortex-M3
- Cortex-M4
- Cortex-M7
- Cortex-R4
- Cortex-R52
- Cortex-R5
- Cortex-R7
- Cortex-R8
- Neoverse N1
- SecurCore SC000
- SecurCore SC100
- SecurCore SC300
Cavium[edit]
IBM[edit]
POWER:
Cell:
Z:
Intel[edit]
Mainstream (x86):
ULP (x86):
MCU:
ULP (ARM):
Server (EPIC) (Itanium):
GPU:
Loongson[edit]
Marvell[edit]
Nvidia[edit]
Qualcomm[edit]
Samsung[edit]
