Semiconductor & Computer Engineering
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Difference between revisions of "lake"
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| Line 3: | Line 3: | ||
* Intel | * Intel | ||
** Microarchitectures | ** Microarchitectures | ||
| + | *** Edge | ||
| + | **** {{intel|Lakefield|l=arch}} | ||
*** Client | *** Client | ||
**** {{intel|Skylake (client)|Skylake|l=arch}} | **** {{intel|Skylake (client)|Skylake|l=arch}} | ||
| Line 12: | Line 14: | ||
**** {{intel|Cannon Lake|l=arch}} | **** {{intel|Cannon Lake|l=arch}} | ||
**** {{intel|Ice Lake (client)|Ice Lake|l=arch}} | **** {{intel|Ice Lake (client)|Ice Lake|l=arch}} | ||
| − | **** {{intel|Tiger Lake|l=arch}} | + | **** {{intel|Tiger Lake|l=arch}} |
*** Server | *** Server | ||
**** {{intel|Skylake (server)|Skylake|l=arch}} | **** {{intel|Skylake (server)|Skylake|l=arch}} | ||
| Line 18: | Line 20: | ||
**** {{intel|Cooper Lake|l=arch}} | **** {{intel|Cooper Lake|l=arch}} | ||
**** {{intel|Ice Lake (server)|Ice Lake|l=arch}} | **** {{intel|Ice Lake (server)|Ice Lake|l=arch}} | ||
| + | *** MCU | ||
| + | **** {{intel|Lakemont|l=arch}} | ||
** Cores | ** Cores | ||
| − | *** {{intel|Apollo Lake|l=core}} | + | *** Client |
| − | *** {{intel|Gemini Lake|l=core}} | + | **** {{intel|Apollo Lake|l=core}} |
| − | *** {{intel|Mercury Lake|l=core}} | + | **** {{intel|Gemini Lake|l=core}} |
| − | *** {{intel|Elkhart Lake|l= | + | **** {{intel|Mercury Lake|l=core}} |
| + | **** {{intel|Elkhart Lake|l=core}} | ||
| + | **** Skylake | ||
| + | ***** {{intel|Skylake DT|l=core}} | ||
| + | ***** {{intel|Skylake S|l=core}} | ||
| + | ***** {{intel|Skylake H|l=core}} | ||
| + | ***** {{intel|Skylake U|l=core}} | ||
| + | ***** {{intel|Skylake Y|l=core}} | ||
| + | *** Kaby Lake | ||
| + | ***** {{intel|Kaby Lake X|l=core}} | ||
| + | ***** {{intel|Kaby Lake DT|l=core}} | ||
| + | ***** {{intel|Kaby Lake R|l=core}} | ||
| + | ***** {{intel|Kaby Lake S|l=core}} | ||
| + | ***** {{intel|Kaby Lake G|l=core}} | ||
| + | ***** {{intel|Kaby Lake H|l=core}} | ||
| + | ***** {{intel|Kaby Lake U|l=core}} | ||
| + | ***** {{intel|Kaby Lake Y|l=core}} | ||
| + | *** Coffee Lake | ||
| + | ***** {{intel|Coffee Lake ER|l=core}} | ||
| + | ***** {{intel|Coffee Lake E|l=core}} | ||
| + | ***** {{intel|Coffee Lake R|l=core}} | ||
| + | ***** {{intel|Coffee Lake S|l=core}} | ||
| + | ***** {{intel|Coffee Lake HR|l=core}} | ||
| + | ***** {{intel|Coffee Lake H|l=core}} | ||
| + | ***** {{intel|Coffee Lake U|l=core}} | ||
| + | *** Whiskey Lake | ||
| + | **** {{intel|Whiskey Lake U|l=core}} | ||
| + | *** Amber Lake | ||
| + | **** {{intel|Amber Lake Y|l=core}} | ||
| + | *** Ice Lake | ||
| + | **** {{intel|Ice Lake U|l=core}} | ||
| + | **** {{intel|Ice Lake Y|l=core}} | ||
| + | *** Server | ||
| + | **** Skylake | ||
| + | ***** {{intel|Skylake SP|l=core}} | ||
| + | ***** {{intel|Skylake X|l=core}} | ||
| + | ***** {{intel|Skylake W|l=core}} | ||
| + | ***** {{intel|Skylake DE|l=core}} | ||
| + | **** Cascade Lake | ||
| + | ***** {{intel|Cascade Lake AP|l=core}} | ||
| + | ***** {{intel|Cascade Lake SP|l=core}} | ||
| + | ***** {{intel|Cascade Lake R|l=core}} | ||
| + | ***** {{intel|Cascade Lake X|l=core}} | ||
| + | ***** {{intel|Cascade Lake W|l=core}} | ||
| + | **** Ice Lake | ||
| + | ***** {{intel|Ice Lake SP|l=core}} | ||
** IGPs | ** IGPs | ||
*** {{intel|Ironlake}} | *** {{intel|Ironlake}} | ||
| + | ** Platforms | ||
| + | *** {{intel|Rock Lake|l=platform}} | ||
* Intel Nervana | * Intel Nervana | ||
** {{nervana|Lake Crest|l=arch}} | ** {{nervana|Lake Crest|l=arch}} | ||
Revision as of 11:52, 31 May 2020
Lake may refer to:
- Intel
- Microarchitectures
- Edge
- Client
- Server
- MCU
- Cores
- Client
- Kaby Lake
- Coffee Lake
- Whiskey Lake
- Amber Lake
- Ice Lake
- Server
- Skylake
- Cascade Lake
- Ice Lake
- IGPs
- Platforms
- Microarchitectures
- Intel Nervana
 |
This is a disambiguation page used to distinguish between articles with similar names. If an internal link led you here, you may wish to change the link to point directly to the intended article. |
