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− | {{title|Kibibyte (KiB) | + | {{title|Kibibyte (KiB)}} |
A '''kibibyte''' ('''KiB'''), derived from ''[[wikipedia:kilo-|kilo]]-[[binary]]-byte'', is a unit of digital information storage equal to 1024 [[bytes]]. This is in contrast to a [[kilobyte]], meaning 1000 bytes. The unit was established by the [[International Electrotechnical Commission]] in [[1998]] to differentiate units in base 10 from units in base 2. IEC formally added it to {{iec|60027-2|IEC 60027-2}} which was later superseded by {{iec|80000-13|IEC 80000-13}}. | A '''kibibyte''' ('''KiB'''), derived from ''[[wikipedia:kilo-|kilo]]-[[binary]]-byte'', is a unit of digital information storage equal to 1024 [[bytes]]. This is in contrast to a [[kilobyte]], meaning 1000 bytes. The unit was established by the [[International Electrotechnical Commission]] in [[1998]] to differentiate units in base 10 from units in base 2. IEC formally added it to {{iec|60027-2|IEC 60027-2}} which was later superseded by {{iec|80000-13|IEC 80000-13}}. | ||
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* A typical [[L1I$]] and [[L1D$]] is between 8 and 64 KiB. For example, [[AMD]]'s {{amd|K5|l=arch}} had 16 KiB L1 instruction cache and 8 KiB data cache. | * A typical [[L1I$]] and [[L1D$]] is between 8 and 64 KiB. For example, [[AMD]]'s {{amd|K5|l=arch}} had 16 KiB L1 instruction cache and 8 KiB data cache. | ||
* A typical [[L2$]] is between 64 and 512 KiB. For example [[Intel]]'s {{intel|Haswell|l=arch}} had 256 KiB of L2 cache. | * A typical [[L2$]] is between 64 and 512 KiB. For example [[Intel]]'s {{intel|Haswell|l=arch}} had 256 KiB of L2 cache. | ||
− | * A 16-bit | + | * A 16-bit CPU cannot directly address more than 64 KiB. |