Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "io wall"
| Line 1: | Line 1: | ||
{{title|I/O Wall}} | {{title|I/O Wall}} | ||
| − | '''I/O [[Wall]]''' refers to a critical performance bottleneck that occurs as a result of the microprocessor's inability to move data fast enough via [[I/O]] to cope with the increase in processing power. This problem is a result of the disparity between the performance | + | '''I/O [[Wall]]''' refers to a critical performance bottleneck that occurs as a result of the microprocessor's inability to move data fast enough via [[I/O]] to cope with the increase in processing power. This problem is a result of the disparity between the performance of the microprocessor and various other network and storage devices. |
| + | |||
| + | == Cause == | ||
| + | The I/O Wall is a result of the disparity between the performance of the processor and the various I/O network and storage devices. | ||
| + | |||
| + | * Power-limited - Insufficient amount of power budget to move enough data quickly enough | ||
| + | * Pin-limited - Insufficient amount of pins to move all the data necessary | ||
Latest revision as of 23:46, 15 January 2018
I/O Wall refers to a critical performance bottleneck that occurs as a result of the microprocessor's inability to move data fast enough via I/O to cope with the increase in processing power. This problem is a result of the disparity between the performance of the microprocessor and various other network and storage devices.
Cause[edit]
The I/O Wall is a result of the disparity between the performance of the processor and the various I/O network and storage devices.
- Power-limited - Insufficient amount of power budget to move enough data quickly enough
- Pin-limited - Insufficient amount of pins to move all the data necessary
