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− | The Vth point of a CMOS inverter can be approximated using the expression \( V_{th} = \frac{V_{DD}-|V_{tp}|+V_{th}\sqrt{\frac{K_n}{K_p}}}{1+\sqrt{\frac{K_n}{K_p}}} \) where \( V_{tn} \) and \( V_{tp} \) are the threshold voltages for nMOS and pMOS devices. \( K_n = (\frac{W}{L})_n \centerdot µ\text{N Cox} \) and \( K_p = (\frac{W}{L})_p \centerdot µ\text{P Cox} \). This equation, however, requires caution as it's not practical for the design process due to non-ideal effects (eg. [[short-channel effect|short-channel effects]]). The static | + | The Vth point of a CMOS inverter can be approximated using the expression \( V_{th} = \frac{V_{DD}-|V_{tp}|+V_{th}\sqrt{\frac{K_n}{K_p}}}{1+\sqrt{\frac{K_n}{K_p}}} \) where \( V_{tn} \) and \( V_{tp} \) are the threshold voltages for nMOS and pMOS devices. \( K_n = (\frac{W}{L})_n \centerdot µ\text{N Cox} \) and \( K_p = (\frac{W}{L})_p \centerdot µ\text{P Cox} \). This equation, however, requires caution as it's not practical for the design process due to non-ideal effects (eg. [[short-channel effect|short-channel effects]]). The static power dissipation during logic 0 and logic 1 are almost zero because \( i_{DP} = i_{DN} = 0 \). When the input is LOW, pMOS is conducting and nMOS is off; the load capacitor is charged via the pMOS device.The power dissipated in the pMOS transistor is \( P_p = i_LV_{P} = i_L(V_{DD}-V_O) \). Likewise, the current can be related by \( i_L = \frac{C_Ldv_O}{dt} \). The energy dissipation in the pMOS device can be expressed as the output switches from LOW to HIGH, |
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</math>, where \( E_p \) is the energy stored in capacitor \( C_L \) during HIGH output. | </math>, where \( E_p \) is the energy stored in capacitor \( C_L \) during HIGH output. | ||
− | When the inverter's input is HIGH and the output is LOW, all the energy stored in the load capacitor is dissipated in the nMOS device because during that time the pMOS is cut off and the nMOS device is conducting. Therefore the energy dissipated in the nMOS device can be expressed as \( E_n = \frac{1}{2}C_LV_{DD}^2 \). During one complete switch cycle the total energy is the sum of both transistors: \( E_T = E_p + E_n = \frac{1}{2}C_LV_{DD}^2 + \frac{1}{2}C_LV_{DD}^2 = C_LV_{DD}^2 \). The power dissipated in terms of | + | When the inverter's input is HIGH and the output is LOW, all the energy stored in the load capacitor is dissipated in the nMOS device because during that time the pMOS is cut off and the nMOS device is conducting. Therefore the energy dissipated in the nMOS device can be expressed as \( E_n = \frac{1}{2}C_LV_{DD}^2 \). During one complete switch cycle the total energy is the sum of both transistors: \( E_T = E_p + E_n = \frac{1}{2}C_LV_{DD}^2 + \frac{1}{2}C_LV_{DD}^2 = C_LV_{DD}^2 \). The power dissipated in terms of frequency can be expressed as \( E_T = P \centerdot t \); \( P = \frac{E_T}{t} \); \( P = fE_T \); \( P = fC_LV_{DD}^2 \). Which shows that the switching frequency and \( V_{DD}^2 \) are directly proportional to the power dissipation of a CMOS inverter. The dynamic capacitive power is \( P_{dyn} = C_LV_{DD}^2f \). |
== VHDL Implementation == | == VHDL Implementation == |