Revision history of "intrinsity/fastmath/fastmath-2"

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(cur | prev) 16:30, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,237 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 18:52, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,236 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 23:02, 23 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,236 bytes) (-27)‎ . . (Bot: Automated text replacement (-\| electrical += Yes +)) (undo)
(cur | prev) 03:39, 23 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,263 bytes) (+1)‎ . . (Bot: corrected mem) (undo)
(cur | prev) 23:50, 20 September 2016‎ ChipIt (talk | contribs)‎ . . (3,262 bytes) (-48)‎ . . (undo)
(cur | prev) 17:45, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,310 bytes) (+29)‎ . . (undo)
(cur | prev) 17:32, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,281 bytes) (+3)‎ . . (undo)
(cur | prev) 17:32, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,278 bytes) (+95)‎ . . (undo)
(cur | prev) 17:28, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,183 bytes) (+4)‎ . . (undo)
(cur | prev) 17:21, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,179 bytes) (+10)‎ . . (undo)
(cur | prev) 17:14, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,169 bytes) (+1,063)‎ . . (undo)
(cur | prev) 16:49, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (2,106 bytes) (+1,856)‎ . . (undo)
(cur | prev) 16:25, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (250 bytes) (+250)‎ . . (Created page with "{{intrinsity title|FastMATH 2 GHz}} The '''FastMATH 2 GHz''' was the flagship microprocessor developed by Intrinsity operating at 2 GHz. The processor incorporates a high-...")

base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed	500 MHz (0.5 GHz, 500,000 kHz) +
bus type	RapidIO +
core count	1 +
core voltage	1 V (10 dV, 100 cV, 1,000 mV) +
designer	Intrinsity +
family	FastMATH +
first announced	2001 +
first launched	2002 +
full page name	intrinsity/fastmath/fastmath-2 +
has feature	JTAG +
instance of	microprocessor +
l1d$ description	256 blocks × 16 words/block +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	256 blocks × 16 words/block +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	2002 +
manufacturer	TSMC +
market segment	Embedded +
max memory	1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitecture	FashMATH +
model number	FastMATH-2 +
name	FastMATH 2 GHz +
power dissipation	15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
technology	Dynamic CMOS +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +

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