Revision history of "intrinsity/fastmath/fastmath-1.5"

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(cur | prev) 16:30, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (3,240 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 18:51, 30 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,239 bytes) (0)‎ . . (Bot: corrected param) (undo)
(cur | prev) 23:02, 23 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,239 bytes) (-27)‎ . . (Bot: Automated text replacement (-\| electrical += Yes +)) (undo)
(cur | prev) 03:39, 23 June 2017‎ ChippyBot (talk | contribs)‎ m . . (3,266 bytes) (+1)‎ . . (Bot: corrected mem) (undo)
(cur | prev) 23:50, 20 September 2016‎ ChipIt (talk | contribs)‎ . . (3,265 bytes) (-48)‎ . . (undo)
(cur | prev) 17:45, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,313 bytes) (+31)‎ . . (undo)
(cur | prev) 17:32, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,282 bytes) (+3)‎ . . (undo)
(cur | prev) 17:32, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,279 bytes) (+95)‎ . . (undo)
(cur | prev) 17:28, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,184 bytes) (+4)‎ . . (undo)
(cur | prev) 17:20, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,180 bytes) (+12)‎ . . (undo)
(cur | prev) 17:14, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (3,168 bytes) (+1,063)‎ . . (undo)
(cur | prev) 16:49, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (2,105 bytes) (+1,860)‎ . . (undo)
(cur | prev) 16:25, 3 July 2016‎ At32Hz (talk | contribs)‎ . . (245 bytes) (+245)‎ . . (Created page with "{{intrinsity title|FastMATH 1.5 GHz}} The '''FastMATH 1.5 GHz''' was a microprocessor developed by Intrinsity operating at 1.5 GHz. The processor incorporates a high-perfo...")

base frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed	500 MHz (0.5 GHz, 500,000 kHz) +
bus type	RapidIO +
core count	1 +
core voltage	1 V (10 dV, 100 cV, 1,000 mV) +
designer	Intrinsity +
family	FastMATH +
first announced	2001 +
first launched	2002 +
full page name	intrinsity/fastmath/fastmath-1.5 +
has feature	JTAG +
instance of	microprocessor +
l1d$ description	256 blocks × 16 words/block +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	256 blocks × 16 words/block +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	2002 +
manufacturer	TSMC +
market segment	Embedded +
max memory	1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitecture	FashMATH +
model number	FastMATH-1.5 +
name	FastMATH 1.5 GHz +
power dissipation	13.5 W (13,500 mW, 0.0181 hp, 0.0135 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
technology	Dynamic CMOS +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +

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