Editing intel/xeon w

{{intel title|Xeon W}}
{{ic family
| title             = Xeon W
| image             = 
| caption           = 
| no image          = Yes
| developer         = Intel
| manufacturer      = Intel
| type              = microprocessors
| first announced   = August 29, 2017
| first launched    = August 29, 2017
| isa               = x86-64
| microarch         = Skylake
| microarch 2       = Cascade Lake
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 2.3 GHz
| clock max         = 4.0 GHz
| package           = FCLGA-2066 or FCLGA3647
| socket            = Socket R4 or Socket P

| succession       = Yes
| predecessor      = Xeon E5
| predecessor link = intel/xeon e5
| successor        = 
| successor link   = 
}}
'''Xeon W''' is a family of enterprise-class {{arch|64}} multi-core [[x86]] performance workstation microprocessors.

== Overview ==
The Xeon W family targets business and enterprise-class performance workstations, situated below the scalable Xeon family and above the {{intel|Xeon E3}}. Compared to the {{intel|Xeon E3}}, Xeon W come with more cores, more [[PCIe]] lanes, [[ECC]] memory, generally almost all available technologies offered by the chip, volume management and various RAS features.
[[File:intel xeon w intro.jpg|left|100px]]
Introduced in August 2017, the Xeon W family is [[Intel]]'s family of workstation-class processors. Prior to their introduction, this segment was served by {{intel|Xeon E5}} family 1600-series. Prior to {{intel|Skylake (server)|Skylake|l=arch}}, the server segment and high-HEDT as well as workstations shared the same socket. With Skylake, the server segment diverged with the workstations and [[HEDT]] parts having their own [[socket]]. The Xeon W family and the HEDT {{intel|Core i7}}/{{intel|Core i9}} parts share the same socket.

== Naming scheme ==
Xeon W SKUs follow the following naming scheme.

[[File:xeon w naming scheme.svg|600px]]

== Members ==
=== W-2000 ===
The W-2000 series is the mainstream workstation series.

==== W-2100-Series (Skylake) ====
{{main|intel/microarchitectures/skylake (server)|l1=Skylake (server) Microarchitecture}}
Skylake-based Xeon W processors come with all the features enabled and only [[core count]] and {{intel|frequency behavior|frequency}} being the differentiating feature, with the exception of the two low-end models. For the most part, all models come with {{x86|AVX-512}} along with two full execution units, similar to the high-end {{intel|Skylake SP|l=core}} models. All models have 48 [[PCIe]] lanes and have all the following features in common:

* '''Bus:''' DMI 3.0
* '''Mem:''' 512 GiB of quad-channel DDR4-2666 ECC Memory
* '''I/O:''' 48 [[PCIe]] 3.0 Lanes
* '''TDP:''' 120 W / 140 W
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}} with 2 FMA units)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).

Note that ''B'' models appear to be a special variant for [[Apple]]'s iMac Pros.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|11:List of Skylake W-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|Mem Type|%Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake W]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
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 |format=template
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 |userparam=13
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}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake W]]}}
</table>
{{comp table end}}

==== W-2200-Series (Cascade Lake) ====
=== W-3000 ===
Xeon W 3000 series was derived from the SP line of server processors, because those had dies with more than 18 cores. As such this line of processors uses Socket 3647 like the Xeon SP series. Since they are limited to single socket they possess no UPI-Links or Intel Omni-Path.
==== W-3100-Series (Skylake) ====
{{main|intel/microarchitectures/skylake|l1=Skylake Microarchitecture}}
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|12:List of Skylake W-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%{{intel|turbo boost|Turbo}}|%{{intel|turbo boost max|Turbo Max}}|Mem Type|%Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake SP]] [[family::Xeon W]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?intel turbo boost max technology 3 0 frequency#GHz
 |?supported memory type
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake SP]] [[family::Xeon W]]}}
</table>
{{comp table end}}
==== W-3200-Series (Cascade Lake) ====
{{main|intel/microarchitectures/cascade lake|l1=Cascade Lake Microarchitecture}}
In early 2019 Intel launched their W-3200 series processors based on the {{intel|Cascade Lake|l=arch}} microarchitecture. Those processors are fabricated on an enhanced [[14 nm process]] which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference), {{intel|Turbo Boost Max}}, and increased the PCIe lanes to 64. All processors also have the following features in common:

* '''Proc:''' [[14 nm process]]
* '''Bus:''' DMI 3.0
* '''Mem:''' 1 TiB of hexa-channel DDR4-2933 ECC Memory
** "''M''" models have 2 TiB extended memory support
* '''I/O:''' 64 [[PCIe]] 3.0 Lanes
* '''TDP:''' 160 W, 180 W, 205 W
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}} with 2 FMA units)
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Identity Protection}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|Volume Management Device}} (VMD).

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|12:List of Cascade Lake W-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%{{intel|turbo boost|Turbo}}|%{{intel|turbo boost max|Turbo Max}}|Mem Type|%Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]] [[family::Xeon W]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
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 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?intel turbo boost max technology 3 0 frequency#GHz
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=14
 |sort=model number
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]] [[family::Xeon W]]}}
</table>
{{comp table end}}
==== W-3300-Series (Ice Lake) ====
{{main|intel/microarchitectures/ice lake|l1=Ice Lake Microarchitecture}}
{{comp table start}}
<table class="comptable sortable tc4 tc5 tc11">
{{comp table header|main|12:List of Ice Lake W-based Processors}}
{{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%{{intel|turbo boost|Turbo}}|%{{intel|turbo boost max|Turbo Max}}|Mem Type|%Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Ice Lake SP]] [[family::Xeon W]]
 |?full page name
 |?model number
 |?first launched
 |?release price
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?intel turbo boost max technology 3 0 frequency#GHz
 |?supported memory type
 |?max memory#TiB
 |format=template
 |template=proc table 3
 |userparam=14
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 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Ice Lake SP]] [[family::Xeon W]]}}
</table>
{{comp table end}}

== See also ==
* Scalable Xeon ({{intel|Xeon Bronze|Bronze}}, {{intel|Xeon Silver|Silver}})
designer	Intel +
first announced	August 29, 2017 +
first launched	August 29, 2017 +
full page name	intel/xeon w +
instance of	microprocessor family +
instruction set architecture	x86-64 +
main designer	Intel +
manufacturer	Intel +
microarchitecture	Skylake + and Cascade Lake +
name	Xeon W +
package	FCLGA-2066 or FCLGA3647 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	Socket R4 or Socket P +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +