Editing intel/xeon silver/4214r (section)

== Cache ==
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1i desc=8-way set associative
|l1d cache=384 KiB
|l1d break=12x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=12 MiB
|l2 break=12x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Silver 4214R - Intel#pcie +
base frequency	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	24 +
core count	12 +
core family	6 +
core name	Cascade Lake R +
designer	Intel +
family	Xeon Silver +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
full page name	intel/xeon silver/4214r +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	February 24, 2020 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	352.15 K (79 °C, 174.2 °F, 633.87 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4214R +
name	Xeon Silver 4214R +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 705.00 (€ 634.50, £ 571.05, ¥ 72,847.65) + and $ 694.00 (€ 624.60, £ 562.14, ¥ 71,711.02) +
release price (box)	$ 694.00 (€ 624.60, £ 562.14, ¥ 71,711.02) +
release price (tray)	$ 705.00 (€ 634.50, £ 571.05, ¥ 72,847.65) +
series	4200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s +
smp max ways	2 +
socket	LGA-3647 + and Socket P +
supported memory type	DDR4-2400 +
tdp	100 W (100,000 mW, 0.134 hp, 0.1 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +