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'''Xeon Platinum 8256''' is a {{arch|64}} [[4-core]] [[x86]] high-performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Platinum 8256 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 8-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
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'''Xeon Platinum 8256''' is a {{arch|64}} [[quad-core]] [[x86]] high-performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Platinum 8256 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 8-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
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== Cache ==
 +
{{main|intel/microarchitectures/cascade_lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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The Xeon Platinum 8256 features a considerably larger non-default 16.5 MiB of [[L3]], a size that would normally be found on a 12-core part.
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{{cache size
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|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
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|l2 cache=4 MiB
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|l2 break=4x1 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=16.5 MiB
 +
|l3 break=12x1.375 MiB
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|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 03:08, 6 April 2019

Edit Values
Xeon Platinum 8256
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number8256
Part NumberCD8069504194701
S-SpecSRF94
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$7007.00 (tray)
$7014.00 (box)
ShopAmazon
General Specs
FamilyXeon Platinum
Series8200
LockedYes
Frequency3,800 MHz
Turbo Frequency3,900 MHz (1 core)
Clock multiplier38
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads8
Max Memory1 TiB
Multiprocessing
Max SMP8-Way (Multiprocessor)
Electrical
TDP105 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Platinum 8256 is a 64-bit quad-core x86 high-performance server microprocessor introduced by Intel in early 2019. The Platinum 8256 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 8-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.9 GHz.

Cache

Main article: Cascade Lake § Cache

The Xeon Platinum 8256 features a considerably larger non-default 16.5 MiB of L3, a size that would normally be found on a 12-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  4x1 MiB16-way set associativewrite-back

L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back
base frequency3,800 MHz (3.8 GHz, 3,800,000 kHz) +
chipsetLewisburg +
clock multiplier38 +
core count4 +
core family6 +
core nameCascade Lake SP +
core steppingB1 +
cpuid0x50655 +
designerIntel +
familyXeon Platinum +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon platinum/8256 +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max cpu count8 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitectureCascade Lake +
model number8256 +
nameXeon Platinum 8256 +
packageFCLGA-3647 +
part numberCD8069504194701 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 7,007.00 (€ 6,306.30, £ 5,675.67, ¥ 724,033.31) + and $ 7,014.00 (€ 6,312.60, £ 5,681.34, ¥ 724,756.62) +
release price (box)$ 7,014.00 (€ 6,312.60, £ 5,681.34, ¥ 724,756.62) +
release price (tray)$ 7,007.00 (€ 6,306.30, £ 5,675.67, ¥ 724,033.31) +
s-specSRF94 +
series8200 +
smp max ways8 +
socketSocket P + and LGA-3647 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count8 +
turbo frequency (1 core)3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +