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Difference between revisions of "intel/xeon platinum/8170"
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{{intel title|Xeon Platinum 8170}}
 
{{intel title|Xeon Platinum 8170}}
 
{{mpu
 
{{mpu
| future             = Yes
+
|future=Yes
| name               = Xeon Platinum 8170
+
|name=Xeon Platinum 8170
| no image           = Yes
+
|no image=Yes
| image              =
+
|designer=Intel
| image size          =
+
|manufacturer=Intel
| caption            =
+
|model number=8170
| designer           = Intel
+
|part number=CD8067303327601
| manufacturer       = Intel
+
|s-spec=SR37H
| model number       = 8170
+
|market=Server
| part number         = CD8067303327601
+
|first announced=April 25, 2017
| part number 1      =
+
|family=Xeon Platinum
| part number 2      =
+
|series=8100
| s-spec             = SR37H
+
|locked=Yes
| s-spec 2            =
+
|frequency=2.1 GHz
| market             = Server
+
|bus type=DMI 3.0
| first announced     = April 25, 2017
+
|bus links=4
| first launched      =
+
|bus rate=8 GT/s
| last order          =
+
|clock multiplier=21
| last shipment      =
+
|isa=x86-64
| release price      =
+
|isa family=x86
 
+
|microarch=Skylake
| family             = Xeon Platinum
+
|platform=Purley
| series             = 8100
+
|chipset=Lewisburg
| locked             = Yes
+
|core name=Skylake SP
| frequency           = 2.1 GHz
+
|core family=6
| turbo frequency    =
+
|core stepping=H0
| turbo frequency1    =
+
|process=14 nm
| turbo frequency2    =
+
|technology=CMOS
| turbo frequency3    =
+
|die area=<!-- XX mm² -->
| turbo frequency4    =
+
|word size=64 bit
| turbo frequency5    =
+
|core count=26
| turbo frequency6    =
+
|thread count=52
| turbo frequency7    =
+
|max cpus=2
| turbo frequency8    =
+
|v core tolerance=<!-- OR ... -->
| bus type           = DMI 3.0
+
|v io 2=<!-- OR ... -->
| bus speed          =  
+
|temp min=<!-- use TJ/TC whenever possible instead -->
| bus rate           = 8 GT/s
+
|tjunc min=<!-- .. °C -->
| bus links          = 4
+
|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
| clock multiplier   = 21
+
|packaging=Yes
| cpuid              =
+
|package 0=FCLGA-3647
| cpuid 2            =
+
|package 0 type=LGA
 
+
|package 0 pins=3647
| isa family          = x86
+
|socket 0=LGA-3647
| isa                 = x86-64
+
|socket 0 type=LGA
| microarch           = Skylake
 
| platform           = Purley
 
| chipset             = Lewisburg
 
| core name           = Skylake SP
 
| core family         =
 
| core model          =  
 
| core stepping       = H0
 
| process             = 14 nm
 
| transistors        =
 
| technology         = CMOS
 
| die area           = <!-- XX mm² -->
 
| die width          =
 
| die length          =
 
| word size           = 64 bit
 
| core count         = 26
 
| thread count       = 52
 
| max cpus           = 2
 
| max memory          =
 
 
 
| electrical          =
 
| power              =
 
| average power      =
 
| idle power          =
 
| v core              =
 
| v core tolerance   = <!-- OR ... -->
 
| v core min          =
 
| v core max          =
 
| v io                =
 
| v io tolerance      =
 
| v io 2             = <!-- OR ... -->
 
| v io 3              =
 
| sdp                =
 
| tdp                =
 
| tdp typical        =
 
| ctdp down          =
 
| ctdp down frequency =
 
| ctdp up            =
 
| ctdp up frequency  =
 
| temp min           = <!-- use TJ/TC whenever possible instead -->
 
| temp max            =
 
| tjunc min           = <!-- .. °C -->
 
| tjunc max          =
 
| tcase min          =
 
| tcase max          =
 
| tstorage min        =
 
| tstorage max        =
 
| tambient min        =
 
| tambient max        =
 
 
 
| package module 1    =
 
| package module 2   =  
 
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
 
| packaging           = Yes
 
| package 0           = FCLGA-3647
 
| package 0 type     = LGA
 
| package 0 pins     = 3647
 
| package 0 pitch    =
 
| package 0 width    =
 
| package 0 length    =
 
| package 0 height    =
 
| socket 0           = LGA-3647
 
| socket 0 type       = LGA
 
 
}}
 
}}
 
'''Xeon Platinum 8170''' is a {{arch|64}} [[x86]] high-performance server [[hexacosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 8170 operates at 2.1 GHz.
 
'''Xeon Platinum 8170''' is a {{arch|64}} [[x86]] high-performance server [[hexacosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 8170 operates at 2.1 GHz.

Revision as of 23:55, 29 June 2017

Template:mpu Xeon Platinum 8170 is a 64-bit x86 high-performance server hexacosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 8170 operates at 2.1 GHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.625 MiB
1,664 KiB
1,703,936 B
0.00159 GiB
L1I$832 KiB
0.813 MiB
851,968 B
7.93457e-4 GiB
26x32 KiB8-way set associative 
L1D$832 KiB
0.813 MiB
851,968 B
7.93457e-4 GiB
26x32 KiB8-way set associativewrite-back

L2$26 MiB
26,624 KiB
27,262,976 B
0.0254 GiB
  26x1 MiB16-way set associativewrite-back

L3$35.75 MiB
36,608 KiB
37,486,592 B
0.0349 GiB
  26x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Controllers1
Channels6
Max Bandwidth119.21 GiB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
SMEPOS Guard Technology
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions + and OS Guard +
has intel enhanced speedstep technologytrue +
has intel supervisor mode execution protectiontrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size1.625 MiB (1,664 KiB, 1,703,936 B, 0.00159 GiB) +
l1d$ description8-way set associative +
l1d$ size0.813 MiB (832 KiB, 851,968 B, 7.93457e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.813 MiB (832 KiB, 851,968 B, 7.93457e-4 GiB) +
l2$ description16-way set associative +
l2$ size26 MiB (26,624 KiB, 27,262,976 B, 0.0254 GiB) +
l3$ description11-way set associative +
l3$ size35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) +
supported memory typeDDR4-2666 +