Editing intel/xeon platinum

{{intel title|Xeon Platinum}}
{{ic family
| title             = Xeon Platinum
| image             = xeon platinum (2017).png
| caption           = Xeon Platinum Logo
| developer         = Intel
| manufacturer      = Intel
| type              = Microprocessors
| first announced   = May 4, 2017
| first launched    = July 11, 2017
| arch              = x86 server multiprocessors
| isa               = x86-64
| microarch         = Skylake
| microarch 2       = Cascade Lake
| microarch 3       = Cooper Lake
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 2,000 MHz
| clock max         = 3,600 MHz
| package           = FCLGA-3647
| socket            = LGA-3647

| succession         = Yes
| predecessor        = Xeon E7
| predecessor link   = intel/xeon e7
| predecessor 2      = Xeon E5
| predecessor 2 link = intel/xeon e5
| successor          = 
| successor link     = 
}}
'''Xeon Platinum''' is a family of {{arch|64}} [[x86]] multi-socket multi-core highest performance server microprocessors introduced by [[Intel]] in 2017. The Xeon Platinum series offers the highest performance, highest scalability, and highest flexibility. 

== Overview ==
Introduced in May [[2017]], the Xeon Platinum family replaces the {{\\|Xeon E7}} and the {{\\|Xeon E5}} families. Xeon Platinum provides the highest performance and flexibility out of all the Xeon families, thus placing it above the {{\\|Xeon Gold}} and {{\\|Xeon Silver}} that were introduced around the same time. A specific feature available only to Platinum models is its eight-way multiprocessing support.

== Members ==
=== 8000-Series ===
==== 8100-Series (Skylake) ====
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
First-generation Xeon Platinum processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the platinum 8100-series microprocessors feature eight-way [[SMP]] capabilities with up to [[28 cores]] and 56 threads. Additionally, all Xeon Platinum processors support:

* '''Proc:''' [[14 nm process]]
* '''TDP:''' 105 W - 205 W
* '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory.
** ''M'' versions support 1.5 TiB per socket
* '''I/O:''' 48 PCIe Gen 3.0 lanes
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}})
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).

All Xeon Platinum processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 3 {{intel|Ultra Path Interconnect}} (UPI) links.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5">
{{comp table header|main|11:List of Skylake-based Xeon Platinum Processors}}
{{comp table header|main|7:Main processor|2:Cache|2:Memory}}
{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l2$ size
 |?l3$ size
 |?supported memory type
 |?max memory#GiB
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake]]}}
</table>
{{comp table end}}

==== 8200-Series (Cascade Lake) ====
{{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}}
Second-generation Xeon Scalable Platinum was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 8200-series Xeon Platinum processors support:

* '''Proc:''' [[14 nm process]]
* '''TDP:''' 105 W - 205 W
* '''Mem:''' 1 TiB hexa-channel DDR4-2933 ECC memory
** ''M'' versions support 2 TiB per socket
** ''L'' versions support 4.5 TiB per socket
* '''I/O:''' 48 PCIe Gen 3.0 lanes
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).

All Xeon Platinum processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 3 {{intel|Ultra Path Interconnect}} (UPI) links.

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc4 tc5">
{{comp table header|main|11:List of Cascade Lake-based Xeon Platinum Processors}}
{{comp table header|main|7:Main processor|2:Cache|2:Memory}}
{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Cascade Lake]] [[series::8200]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l2$ size
 |?l3$ size
 |?supported memory type
 |?max memory#GiB
 |format=template
 |template=proc table 3
 |valuesep=,
 |userparam=13
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Cascade Lake]] [[series::8200]]}}
</table>
{{comp table end}}

=== 9000-Series ===
==== 9200-Series (Cascade Lake) ====
[[File:cascade lake ap board.JPG|right|thumb|Cascade Lake AP S9200WK module]]
{{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}}
Along with its mainstream second-generation Xeon Scalable Platinum processors, Intel introduced the 9200 series, codenamed {{intel|Cascade Lake AP|l=core}}. The chips incorporate multiple {{intel|Cascade Lake|l=arch}} dies in a [[multi-chip package]], enabling up to 56 cores in a single socket. In other words, the 9200 series incorporates two 8200 series chips in a single socket, doubling the density. It's important to note that those processors cannot be purchased individually. Instead, they can only be bought as part of Intel's S9200WK compute module which is essentially a complete system designed by Intel. 

* '''Proc:''' [[14 nm process]]
* '''TDP:''' 250 W - 400 W
* '''Mem:''' 2 TiB hexa-channel DDR4-2933 ECC memory
* '''I/O:''' x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently)
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc3 tc4 tc5 tc6">
{{comp table header|main|11:List of Cascade Lake AP-based Xeon Platinum Processors}}
{{comp table header|main|7:Main processor|2:Cache|2:Memory}}
{{comp table header 1|cols=Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
{{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]
 |?full page name
 |?model number
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?l2$ size
 |?l3$ size
 |?supported memory type
 |?max memory#GiB
 |format=template
 |template=proc table 3
 |valuesep=,
 |userparam=12
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]}}
</table>
{{comp table end}}

== See also ==
* {{\\|Xeon Bronze}}
* {{\\|Xeon Silver}}
* {{\\|Xeon Gold}}
designer	Intel +
first announced	May 4, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon platinum +
instance of	microprocessor family +
instruction set architecture	x86-64 +
main designer	Intel +
manufacturer	Intel +
microarchitecture	Skylake +, Cascade Lake + and Cooper Lake +
name	Xeon Platinum +
package	FCLGA-3647 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-3647 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +