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{{intel title|Xeon Gold 6254}}
 
{{intel title|Xeon Gold 6254}}
{{chip
+
{{chip}}
|future=Yes
 
|name=Xeon Gold 6254
 
|image=skylake sp (basic).png
 
|designer=Intel
 
|manufacturer=Intel
 
|model number=6254
 
|market=Server
 
|first announced=March, 2019
 
|first launched=March, 2019
 
|family=Xeon Gold
 
|series=6000
 
|locked=Yes
 
|frequency=3,100 MHz
 
|turbo frequency1=4,000 MHz
 
|bus type=DMI 3.0
 
|bus links=4
 
|bus rate=8 GT/s
 
|clock multiplier=31
 
|cpuid=0x50655
 
|isa=x86-64
 
|isa family=x86
 
|microarch=Cascade Lake
 
|platform=Purley
 
|chipset=Lewisburg
 
|core name=Cascade Lake SP
 
|core family=6
 
|process=14 nm
 
|technology=CMOS
 
|word size=64 bit
 
|core count=18
 
|thread count=36
 
|max cpus=4
 
|tdp=200 W
 
|package module 1={{packages/intel/fclga-3647}}
 
}}
 
 
'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6254 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a {{intel|turbo boost}} frequency of up to 4 GHz.
 
'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6254 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a {{intel|turbo boost}} frequency of up to 4 GHz.
 
 
== Cache ==
 
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
{{cache size
 
|l1 cache=1.125 MiB
 
|l1i cache=576 KiB
 
|l1i break=18x32 KiB
 
|l1i desc=8-way set associative
 
|l1d cache=576 KiB
 
|l1d break=18x32 KiB
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l2 cache=18 MiB
 
|l2 break=18x1 MiB
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l3 cache=24.75 MiB
 
|l3 break=18x1.375 MiB
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
}}
 
 
== Memory controller ==
 
{{memory controller
 
|type=DDR4-2933
 
|ecc=Yes
 
|max mem=? GiB
 
|controllers=2
 
|channels=6
 
|max bandwidth=119.21 GiB/s
 
|bandwidth schan=19.87 GiB/s
 
|bandwidth dchan=39.74 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth hchan=119.21 GiB/s
 
}}
 
 
== Expansions ==
 
{{expansions
 
| pcie revision      = 3.0
 
| pcie lanes        = 48
 
| pcie config        = x16
 
| pcie config 2      = x8
 
| pcie config 3      = x4
 
}}
 
 
== Features ==
 
{{x86 features
 
|real=Yes
 
|protected=Yes
 
|smm=Yes
 
|fpu=Yes
 
|x8616=Yes
 
|x8632=Yes
 
|x8664=Yes
 
|nx=Yes
 
|mmx=Yes
 
|emmx=Yes
 
|sse=Yes
 
|sse2=Yes
 
|sse3=Yes
 
|ssse3=Yes
 
|sse41=Yes
 
|sse42=Yes
 
|sse4a=No
 
|avx=Yes
 
|avx2=Yes
 
|avx512f=Yes
 
|avx512cd=Yes
 
|avx512er=No
 
|avx512pf=No
 
|avx512bw=Yes
 
|avx512dq=Yes
 
|avx512vl=Yes
 
|avx512ifma=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|abm=Yes
 
|tbm=No
 
|bmi1=Yes
 
|bmi2=Yes
 
|fma3=Yes
 
|fma4=No
 
|aes=Yes
 
|rdrand=Yes
 
|sha=No
 
|xop=No
 
|adx=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|bfloat16=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbmt3=No
 
|bpt=No
 
|eist=Yes
 
|sst=Yes
 
|flex=No
 
|fastmem=No
 
|ivmd=Yes
 
|intelnodecontroller=Yes
 
|intelnode=Yes
 
|kpt=Yes
 
|ptt=Yes
 
|intelrunsure=Yes
 
|mbe=Yes
 
|isrt=No
 
|sba=No
 
|mwt=No
 
|sipp=No
 
|att=No
 
|ipt=No
 
|tsx=Yes
 
|txt=Yes
 
|ht=Yes
 
|vpro=Yes
 
|vtx=Yes
 
|vtd=Yes
 
|ept=Yes
 
|mpx=No
 
|sgx=No
 
|securekey=No
 
|osguard=No
 
|intqat=No
 
|dlboost=Yes
 
|3dnow=No
 
|e3dnow=No
 
|smartmp=No
 
|powernow=No
 
|amdvi=No
 
|amdv=No
 
|amdsme=No
 
|amdtsme=No
 
|amdsev=No
 
|rvi=No
 
|smt=No
 
|sensemi=No
 
|xfr=No
 
|xfr2=No
 
|mxfr=No
 
|amdpb=No
 
|amdpb2=No
 
|amdpbod=No
 
}}
 

Revision as of 21:49, 7 May 2019

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General Info
Microarchitecture

Xeon Gold 6254 is a 64-bit 18-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6254 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a turbo boost frequency of up to 4 GHz.

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