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Difference between revisions of "intel/xeon gold/6161"
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{{intel title|Xeon Gold 6161}}
 
{{intel title|Xeon Gold 6161}}
 
{{mpu
 
{{mpu
| future             = Yes
+
|future=Yes
| name               = Xeon Gold 6161
+
|name=Xeon Gold 6161
| no image           = Yes
+
|no image=Yes
| image              =
+
|designer=Intel
| image size          =
+
|manufacturer=Intel
| caption            =
+
|model number=6161
| designer           = Intel
+
|market=Server
| manufacturer       = Intel
+
|family=Xeon Gold
| model number       = 6161
+
|series=6100
| part number        =
+
|locked=Yes
| part number 1      =
+
|frequency=2,200 MHz
| part number 2      =
+
|turbo frequency1=3,000 MHz
| s-spec              =
+
|bus type=DMI 3.0
| s-spec 2            =
+
|bus links=4
| market             = Server
+
|bus rate=8 GT/s
| first announced    =
+
|clock multiplier=22
| first launched      =
+
|isa=x86-64
| last order          =
+
|isa family=x86
| last shipment      =
+
|microarch=Skylake
| release price      =
+
|platform=Purley
 
+
|chipset=Lewisburg
| family             = Xeon Gold
+
|core name=Skylake SP
| series             = 6100
+
|core family=6
| locked             = Yes
+
|core stepping=H0
| frequency           = 2,200 MHz
+
|process=14 nm
| turbo frequency    = Yes
+
|technology=CMOS
| turbo frequency1   = 3,000 MHz
+
|die area=<!-- XX mm² -->
| turbo frequency2    =
+
|word size=64 bit
| turbo frequency3    =
+
|core count=22
| turbo frequency4    =
+
|thread count=44
| turbo frequency5    =
+
|max cpus=2
| turbo frequency6    =
+
|v core tolerance=<!-- OR ... -->
| turbo frequency7    =
+
|v io 2=<!-- OR ... -->
| turbo frequency8    =
+
|tdp=165 W
| bus type           = DMI 3.0
+
|temp min=<!-- use TJ/TC whenever possible instead -->
| bus speed          =  
+
|tjunc min=<!-- .. °C -->
| bus rate           = 8 GT/s
+
|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
| bus links          = 4
+
|turbo frequency=Yes
| clock multiplier   = 22
+
|packaging=Yes
| cpuid              =
+
|package 0=FCLGA-3647
| cpuid 2            =
+
|package 0 type=LGA
 
+
|package 0 pins=3647
| isa family          = x86
+
|socket 0=LGA-3647
| isa                 = x86-64
+
|socket 0 type=LGA
| microarch           = Skylake
 
| platform           = Purley
 
| chipset             = Lewisburg
 
| core name           = Skylake SP
 
| core family         =
 
| core model          =  
 
| core stepping       = H0
 
| process             = 14 nm
 
| transistors        =
 
| technology         = CMOS
 
| die area           = <!-- XX mm² -->
 
| die width          =
 
| die length          =
 
| word size           = 64 bit
 
| core count         = 22
 
| thread count       = 44
 
| max cpus           = 2
 
| max memory          =
 
 
 
| electrical          =
 
| power              =
 
| average power      =
 
| idle power          =
 
| v core              =
 
| v core tolerance   = <!-- OR ... -->
 
| v core min          =
 
| v core max          =
 
| v io                =
 
| v io tolerance      =
 
| v io 2             = <!-- OR ... -->
 
| v io 3              =
 
| sdp                =
 
| tdp                 = 165 W
 
| tdp typical        =
 
| ctdp down          =
 
| ctdp down frequency =
 
| ctdp up            =
 
| ctdp up frequency  =
 
| temp min           = <!-- use TJ/TC whenever possible instead -->
 
| temp max            =
 
| tjunc min           = <!-- .. °C -->
 
| tjunc max          =
 
| tcase min          =
 
| tcase max          =
 
| tstorage min        =
 
| tstorage max        =
 
| tambient min        =
 
| tambient max        =
 
 
 
| package module 1    =
 
| package module 2   =  
 
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
 
| packaging           = Yes
 
| package 0           = FCLGA-3647
 
| package 0 type     = LGA
 
| package 0 pins     = 3647
 
| package 0 pitch    =
 
| package 0 width    =
 
| package 0 length    =
 
| package 0 height    =
 
| socket 0           = LGA-3647
 
| socket 0 type       = LGA
 
 
}}
 
}}
 
'''Xeon Gold 6161''' is a {{arch|64}} [[x86]] high-performance server [[docosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6161 operates at 2.2 GHz with a TDP of 165 W and a {{intel|Turbo Boost|turbo frequency}} of 3 GHz.
 
'''Xeon Gold 6161''' is a {{arch|64}} [[x86]] high-performance server [[docosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6161 operates at 2.2 GHz with a TDP of 165 W and a {{intel|Turbo Boost|turbo frequency}} of 3 GHz.

Revision as of 00:57, 30 June 2017

Template:mpu Xeon Gold 6161 is a 64-bit x86 high-performance server docosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6161 operates at 2.2 GHz with a TDP of 165 W and a turbo frequency of 3 GHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.375 MiB
1,408 KiB
1,441,792 B
L1I$704 KiB
720,896 B
0.688 MiB
22x32 KiB8-way set associative 
L1D$704 KiB
720,896 B
0.688 MiB
22x32 KiB8-way set associativewrite-back

L2$22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
  22x1 MiB16-way set associativewrite-back

L3$30.25 MiB
30,976 KiB
31,719,424 B
0.0295 GiB
  22x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Controllers1
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
EISTEnhanced SpeedStep Technology
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
SMEPOS Guard Technology
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard +
has intel enhanced speedstep technologytrue +
has intel supervisor mode execution protectiontrue +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size1,408 KiB (1,441,792 B, 1.375 MiB) +
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description16-way set associative +
l2$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
l3$ description11-way set associative +
l3$ size30.25 MiB (30,976 KiB, 31,719,424 B, 0.0295 GiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
supported memory typeDDR4-2666 +
x86/has memory protection extensionstrue +