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Difference between revisions of "intel/xeon gold/6138"
< intel‎ | xeon gold

(more info from engineering samples)
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|l3 cache=27.5 MiB
 
|l3 cache=27.5 MiB
 
|l3 break=20x1.375 MiB
 
|l3 break=20x1.375 MiB
|l3 desc=16-way set associative
+
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
 
}}
 
}}

Revision as of 09:48, 4 June 2017

Template:mpu Xeon Gold 6138 is a 64-bit x86 high-performance server icosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6138 operates at 2.0 GHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.25 MiB
1,280 KiB
1,310,720 B
0.00122 GiB
L1I$640 KiB
0.625 MiB
655,360 B
6.103516e-4 GiB
20x32 KiB8-way set associative 
L1D$640 KiB
0.625 MiB
655,360 B
6.103516e-4 GiB
20x32 KiB8-way set associativewrite-back

L2$20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
  20x1 MiB16-way set associativewrite-back

L3$27.5 MiB
28,160 KiB
28,835,840 B
0.0269 GiB
  20x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Controllers1
Channels6
Max Bandwidth119.21 GiB/s
207.425 GB/s
122,071.04 MiB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
has ecc memory supporttrue +
l1$ size1.25 MiB (1,280 KiB, 1,310,720 B, 0.00122 GiB) +
l1d$ description8-way set associative +
l1d$ size0.625 MiB (640 KiB, 655,360 B, 6.103516e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.625 MiB (640 KiB, 655,360 B, 6.103516e-4 GiB) +
l2$ description16-way set associative +
l2$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description11-way set associative +
l3$ size27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
max memory bandwidth119.21 GiB/s (207.425 GB/s, 122,071.04 MiB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
supported memory typeDDR4-2666 +