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{{intel title|Xeon Gold 6138}}
 
{{intel title|Xeon Gold 6138}}
{{chip
+
{{mpu
 +
|future=Yes
 
|name=Xeon Gold 6138
 
|name=Xeon Gold 6138
|image=skylake sp (basic).png
+
|no image=Yes
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=6138
 
|model number=6138
|part number=BX806736138
+
|part number=CD8067303406100
|part number 2=CD8067303406100
 
 
|s-spec=SR3B5
 
|s-spec=SR3B5
|s-spec qs=QMS0
 
 
|market=Server
 
|market=Server
 
|first announced=April 25, 2017
 
|first announced=April 25, 2017
|first launched=July 11, 2017
 
|release price=$2612.00
 
 
|family=Xeon Gold
 
|family=Xeon Gold
 
|series=6100
 
|series=6100
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|bus rate=8 GT/s
 
|bus rate=8 GT/s
 
|clock multiplier=20
 
|clock multiplier=20
|cpuid=0x50654
 
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
|microarch=Skylake (server)
+
|microarch=Skylake
 
|platform=Purley
 
|platform=Purley
 
|chipset=Lewisburg
 
|chipset=Lewisburg
Line 34: Line 30:
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|die area=<!-- XX mm² -->
 
|word size=64 bit
 
|word size=64 bit
 
|core count=20
 
|core count=20
 
|thread count=40
 
|thread count=40
|max memory=768 GiB
+
|max cpus=2
|max cpus=4
+
|v core tolerance=<!-- OR ... -->
|smp interconnect=UPI
+
|v io 2=<!-- OR ... -->
|smp interconnect links=3
+
|tdp=145 W
|smp interconnect rate=10.4 GT/s
+
|temp min=<!-- use TJ/TC whenever possible instead -->
|tdp=125 W
+
|tjunc min=<!-- .. °C -->
|tcase min=0 °C
+
|package module 2=<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
|tcase max=86 °C
+
|turbo frequency=Yes
|dts min=0 °C
+
|package module 1={{packages/intel/fclga-3647}}
|dts max=93 °C
 
|package name 1=intel,fclga_3647
 
|successor=Xeon Gold 6238
 
|successor link=intel/xeon_gold/6238
 
 
}}
 
}}
'''Xeon Gold 6138''' is a {{arch|64}} [[20-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6138, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
+
'''Xeon Gold 6138''' is a {{arch|64}} [[x86]] high-performance server [[icosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6138 operates at 2.0 GHz with a TDP of 145 W and a {{intel|Turbo Boost|turbo frequency}} of 3.7 GHz.
 +
 
 +
 
 +
{{unknown features}}
  
 
== Cache ==
 
== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
 
|l1 cache=1.25 MiB
 
|l1 cache=1.25 MiB
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|type=DDR4-2666
 
|type=DDR4-2666
 
|ecc=Yes
 
|ecc=Yes
|max mem=768 GiB
+
|max mem=
|controllers=2
+
|controllers=1
 
|channels=6
 
|channels=6
 
|max bandwidth=119.21 GiB/s
 
|max bandwidth=119.21 GiB/s
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=19.89 GiB/s
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=39.72 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth hchan=119.21 GiB/s
 
|bandwidth hchan=119.21 GiB/s
}}
 
 
== Expansions ==
 
{{expansions
 
| pcie revision      = 3.0
 
| pcie lanes        = 48
 
| pcie config        = x16
 
| pcie config 2      = x8
 
| pcie config 3      = x4
 
 
}}
 
}}
  
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|avx=Yes
 
|avx=Yes
 
|avx2=Yes
 
|avx2=Yes
|avx512f=Yes
+
|avx512=Yes
|avx512cd=Yes
 
|avx512er=No
 
|avx512pf=No
 
|avx512bw=Yes
 
|avx512dq=Yes
 
|avx512vl=Yes
 
|avx512ifma=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
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|f16c=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt1=No
|tbt2=Yes
+
|tbt2=No
 
|tbmt3=No
 
|tbmt3=No
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
|sst=Yes
+
|sst=No
 
|flex=No
 
|flex=No
 
|fastmem=No
 
|fastmem=No
|ivmd=Yes
 
|intelnodecontroller=Yes
 
|intelnode=Yes
 
|kpt=Yes
 
|ptt=Yes
 
|intelrunsure=Yes
 
|mbe=Yes
 
 
|isrt=No
 
|isrt=No
 
|sba=No
 
|sba=No
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|ipt=No
 
|ipt=No
 
|tsx=Yes
 
|tsx=Yes
|txt=Yes
+
|txt=No
 
|ht=Yes
 
|ht=Yes
 
|vpro=Yes
 
|vpro=Yes
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|vtd=Yes
 
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
|mpx=No
+
|mpx=Yes
 
|sgx=No
 
|sgx=No
 
|securekey=No
 
|securekey=No
|osguard=No
+
|osguard=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
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|amdvi=No
 
|amdvi=No
 
|amdv=No
 
|amdv=No
|amdsme=No
 
|amdtsme=No
 
|amdsev=No
 
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No
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|xfr=No
 
|xfr=No
 
}}
 
}}
 
== Frequencies ==
 
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
{{frequency table
 
|freq_base=2,000 MHz
 
|freq_1=3,700 MHz
 
|freq_2=3,700 MHz
 
|freq_3=3,500 MHz
 
|freq_4=3,500 MHz
 
|freq_5=3,400 MHz
 
|freq_6=3,400 MHz
 
|freq_7=3,400 MHz
 
|freq_8=3,400 MHz
 
|freq_9=3,200 MHz
 
|freq_10=3,200 MHz
 
|freq_11=3,200 MHz
 
|freq_12=3,200 MHz
 
|freq_13=2,900 MHz
 
|freq_14=2,900 MHz
 
|freq_15=2,900 MHz
 
|freq_16=2,900 MHz
 
|freq_17=2,700 MHz
 
|freq_18=2,700 MHz
 
|freq_19=2,700 MHz
 
|freq_20=2,700 MHz
 
|freq_avx2_base=1,600 MHz
 
|freq_avx2_1=3,600 MHz
 
|freq_avx2_2=3,600 MHz
 
|freq_avx2_3=3,400 MHz
 
|freq_avx2_4=3,400 MHz
 
|freq_avx2_5=3,200 MHz
 
|freq_avx2_6=3,200 MHz
 
|freq_avx2_7=3,200 MHz
 
|freq_avx2_8=3,200 MHz
 
|freq_avx2_9=2,700 MHz
 
|freq_avx2_10=2,700 MHz
 
|freq_avx2_11=2,700 MHz
 
|freq_avx2_12=2,700 MHz
 
|freq_avx2_13=2,500 MHz
 
|freq_avx2_14=2,500 MHz
 
|freq_avx2_15=2,500 MHz
 
|freq_avx2_16=2,500 MHz
 
|freq_avx2_17=2,300 MHz
 
|freq_avx2_18=2,300 MHz
 
|freq_avx2_19=2,300 MHz
 
|freq_avx2_20=2,300 MHz
 
|freq_avx512_base=1,300 MHz
 
|freq_avx512_1=3,500 MHz
 
|freq_avx512_2=3,500 MHz
 
|freq_avx512_3=3,300 MHz
 
|freq_avx512_4=3,300 MHz
 
|freq_avx512_5=2,700 MHz
 
|freq_avx512_6=2,700 MHz
 
|freq_avx512_7=2,700 MHz
 
|freq_avx512_8=2,700 MHz
 
|freq_avx512_9=2,300 MHz
 
|freq_avx512_10=2,300 MHz
 
|freq_avx512_11=2,300 MHz
 
|freq_avx512_12=2,300 MHz
 
|freq_avx512_13=2,000 MHz
 
|freq_avx512_14=2,000 MHz
 
|freq_avx512_15=2,000 MHz
 
|freq_avx512_16=2,000 MHz
 
|freq_avx512_17=1,900 MHz
 
|freq_avx512_18=1,900 MHz
 
|freq_avx512_19=1,900 MHz
 
|freq_avx512_20=1,900 MHz
 
}}
 
 
[[Category:microprocessor models by intel based on skylake extreme core count die]]
 

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Has subobject
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Xeon Gold 6138 - Intel#io +
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier20 +
core count20 +
core family6 +
core nameSkylake SP +
core steppingH0 +
cpuid0x50654 +
designerIntel +
familyXeon Gold +
first announcedApril 25, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold/6138 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description8-way set associative +
l1d$ size640 KiB (655,360 B, 0.625 MiB) +
l1i$ description8-way set associative +
l1i$ size640 KiB (655,360 B, 0.625 MiB) +
l2$ description16-way set associative +
l2$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description11-way set associative +
l3$ size27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldateJuly 11, 2017 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max case temperature359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count4 +
max dts temperature93 °C +
max memory786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureSkylake (server) +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature0 °C +
model number6138 +
nameXeon Gold 6138 +
packageFCLGA-3647 +
part numberCD8067303406100 + and BX806736138 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,612.00 (€ 2,350.80, £ 2,115.72, ¥ 269,897.96) +
s-specSR3B5 +
s-spec (qs)QMS0 +
series6100 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technologyCMOS +
thread count40 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +