Difference between revisions of "intel/xeon gold/5215l"

	Edit Values
	Xeon Gold 5215L
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	5215L
Part Number	CD8069504214202
S-Spec	SRFBD; QRGB (QS)
Market	Server
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Release Price	$4,224.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	5200
Locked	Yes
Frequency	2,500 MHz
Turbo Frequency	3,400 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	25
CPUID	0x50655
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	L0, L1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	20
Max Memory	4.5 TiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	3
Interconnect Rate	10.4 GT/s
	Electrical
TDP	85 W
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Latest revision as of 23:43, 28 December 2019

Xeon Gold 5215L is a 64-bit deca-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5215L is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 4.5 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.

As indicated by the "L" suffix, this model features extended memory support of up to 4.5 TiB of memory.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

640 KiB

655,360 B
0.625 MiB

L1I$	320 KiB 327,680 B 0.313 MiB	10x32 KiB	8-way set associative
L1D$	320 KiB 327,680 B 0.313 MiB	10x32 KiB	8-way set associative	write-back

L2$

10 MiB

10,240 KiB
10,485,760 B
0.00977 GiB

		10x1 MiB	16-way set associative	write-back

L3$

13.75 MiB

14,080 KiB
14,417,920 B
0.0134 GiB

		10x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	4.5 TiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 48
	Configuration: 1x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_VNNI	AVX-512 Vector Neural Network Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control
DL Boost	Deep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10
Normal	2,500MHz	3,400MHz	3,400MHz	3,200MHz	3,200MHz	3,100MHz	3,100MHz	3,100MHz	3,100MHz	3,000MHz	3,000MHz
AVX2	2,000MHz	3,100MHz	3,100MHz	2,900MHz	2,900MHz	2,800MHz	2,800MHz	2,800MHz	2,800MHz	2,600MHz	2,600MHz
AVX512	1,400MHz	2,900MHz	2,900MHz	2,500MHz	2,500MHz	1,900MHz	1,900MHz	1,900MHz	1,900MHz	1,800MHz	1,800MHz

@@ Line 8: / Line 8: @@
 |part number=CD8069504214202
 |s-spec=SRFBD
+|s-spec qs=QRGB
 |market=Server
 |first announced=April 2, 2019
@@ Line 29: / Line 30: @@
 |core name=Cascade Lake SP
 |core family=6
-|core stepping=L1
+|core stepping=L0
+|core stepping 2=L1
 |process=14 nm
 |technology=CMOS
@@ Line 35: / Line 37: @@
 |core count=10
 |thread count=20
+|max memory=4.5 TiB
 |max cpus=4
-|max memory=4.5 TiB
+|smp interconnect=UPI
+|smp interconnect links=3
+|smp interconnect rate=10.4 GT/s
 |tdp=85 W
 |package name 1=intel,fclga_3647
 }}
-'''Xeon Gold 5215L''' is a {{arch|64}} [[deca-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5215L is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 4.5 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
+'''Xeon Gold 5215L''' is a {{arch|64}} [[deca-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5215L is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 4.5 TiB of hexa-channel DDR4-2666 memory, operates at 2.2 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.
 As indicated by the "''L''" suffix, this model features extended memory support of up to 4.5 TiB of memory.
@@ Line 193: / Line 198: @@
 |amdpb2=No
 |amdpbod=No
+}}
+== Frequencies ==
+{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
+{{frequency table
+|freq_base=2,500MHz
+|freq_1=3,400MHz
+|freq_2=3,400MHz
+|freq_3=3,200MHz
+|freq_4=3,200MHz
+|freq_5=3,100MHz
+|freq_6=3,100MHz
+|freq_7=3,100MHz
+|freq_8=3,100MHz
+|freq_9=3,000MHz
+|freq_10=3,000MHz
+|freq_avx2_base=2,000MHz
+|freq_avx2_1=3,100MHz
+|freq_avx2_2=3,100MHz
+|freq_avx2_3=2,900MHz
+|freq_avx2_4=2,900MHz
+|freq_avx2_5=2,800MHz
+|freq_avx2_6=2,800MHz
+|freq_avx2_7=2,800MHz
+|freq_avx2_8=2,800MHz
+|freq_avx2_9=2,600MHz
+|freq_avx2_10=2,600MHz
+|freq_avx512_base=1,400MHz
+|freq_avx512_1=2,900MHz
+|freq_avx512_2=2,900MHz
+|freq_avx512_3=2,500MHz
+|freq_avx512_4=2,500MHz
+|freq_avx512_5=1,900MHz
+|freq_avx512_6=1,900MHz
+|freq_avx512_7=1,900MHz
+|freq_avx512_8=1,900MHz
+|freq_avx512_9=1,800MHz
+|freq_avx512_10=1,800MHz
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5215L - Intel#pcie +
base frequency	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	25 +
core count	10 +
core family	6 +
core name	Cascade Lake SP +
core stepping	L0 + and L1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5215l +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	320 KiB (327,680 B, 0.313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	320 KiB (327,680 B, 0.313 MiB) +
l2$ description	16-way set associative +
l2$ size	10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description	11-way set associative +
l3$ size	13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory	4,718,592 MiB (4,831,838,208 KiB, 4,947,802,324,992 B, 4,608 GiB, 4.5 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	5215L +
name	Xeon Gold 5215L +
package	FCLGA-3647 +
part number	CD8069504214202 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
release price (tray)	$ 4,224.00 (€ 3,801.60, £ 3,421.44, ¥ 436,465.92) +
s-spec	SRFBD +
s-spec (qs)	QRGB +
series	5200 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	20 +
turbo frequency (1 core)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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