Revision history of "intel/xeon gold/5122"

Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.

(cur | prev) 14:54, 12 January 2020‎ 188.36.113.205 (talk)‎ . . (4,325 bytes) (-1)‎ . . (undo)
(cur | prev) 14:53, 12 January 2020‎ 188.36.113.205 (talk)‎ . . (4,326 bytes) (+1)‎ . . (undo)
(cur | prev) 23:47, 28 December 2019‎ David (talk | contribs)‎ . . (4,325 bytes) (+81)‎ . . (undo)
(cur | prev) 01:09, 24 May 2019‎ David (talk | contribs)‎ . . (4,244 bytes) (0)‎ . . (undo)
(cur | prev) 14:14, 8 May 2019‎ ChippyBot (talk | contribs)‎ m . . (4,244 bytes) (-15)‎ . . (replacing old packaging template with new module) (undo)
(cur | prev) 11:47, 8 May 2019‎ David (talk | contribs)‎ . . (4,259 bytes) (+63)‎ . . (undo)
(cur | prev) 19:06, 12 January 2019‎ David (talk | contribs)‎ . . (4,196 bytes) (+158)‎ . . (undo)
(cur | prev) 19:06, 12 January 2019‎ David (talk | contribs)‎ . . (4,038 bytes) (0)‎ . . (undo)
(cur | prev) 23:36, 18 November 2018‎ Inject (talk | contribs)‎ . . (4,038 bytes) (0)‎ . . (undo)
(cur | prev) 23:35, 18 November 2018‎ Inject (talk | contribs)‎ . . (4,038 bytes) (+2)‎ . . (→‎Memory controller) (undo)
(cur | prev) 16:29, 13 December 2017‎ ChippyBot (talk | contribs)‎ m . . (4,036 bytes) (+1)‎ . . (Bot: moving all {{mpu}} to {{chip}}) (undo)
(cur | prev) 08:59, 23 July 2017‎ David (talk | contribs)‎ . . (4,035 bytes) (+32)‎ . . (undo)
(cur | prev) 05:32, 23 July 2017‎ ChippyBot (talk | contribs)‎ m . . (4,003 bytes) (+9)‎ . . (Bot: Automated text replacement (-skylake#Memory_Hierarchy +skylake_(server)#Memory_Hierarchy)) (undo)
(cur | prev) 02:28, 23 July 2017‎ ChippyBot (talk | contribs)‎ m . . (3,994 bytes) (+17)‎ . . (Bot: Automated text replacement (-{{intel|Skylake|l=arch}} +{{intel|Skylake (server)|Skylake|l=arch}})) (undo)
(cur | prev) 02:14, 23 July 2017‎ ChippyBot (talk | contribs)‎ m . . (3,977 bytes) (+9)‎ . . (Bot: Automated text replacement (-|microarch=Skylake +|microarch=Skylake (server))) (undo)
(cur | prev) 01:54, 18 July 2017‎ At32Hz (talk | contribs)‎ . . (3,968 bytes) (+85)‎ . . (undo)
(cur | prev) 01:03, 18 July 2017‎ At32Hz (talk | contribs)‎ . . (3,883 bytes) (+31)‎ . . (undo)
(cur | prev) 00:15, 17 July 2017‎ At32Hz (talk | contribs)‎ . . (3,852 bytes) (+246)‎ . . (undo)
(cur | prev) 23:39, 16 July 2017‎ At32Hz (talk | contribs)‎ . . (3,606 bytes) (+94)‎ . . (undo)
(cur | prev) 23:32, 16 July 2017‎ At32Hz (talk | contribs)‎ . . (3,512 bytes) (+111)‎ . . (undo)
(cur | prev) 20:56, 11 July 2017‎ David (talk | contribs)‎ . . (3,401 bytes) (+949)‎ . . (undo)
(cur | prev) 20:55, 11 July 2017‎ David (talk | contribs)‎ . . (2,452 bytes) (+166)‎ . . (undo)
(cur | prev) 20:52, 11 July 2017‎ David (talk | contribs)‎ . . (2,286 bytes) (-680)‎ . . (undo)
(cur | prev) 20:47, 11 July 2017‎ David (talk | contribs)‎ . . (2,966 bytes) (+137)‎ . . (undo)
(cur | prev) 20:46, 11 July 2017‎ David (talk | contribs)‎ . . (2,829 bytes) (+2)‎ . . (undo)
(cur | prev) 20:45, 11 July 2017‎ David (talk | contribs)‎ . . (2,827 bytes) (-6)‎ . . (→‎Cache) (undo)
(cur | prev) 20:36, 11 July 2017‎ David (talk | contribs)‎ . . (2,833 bytes) (+229)‎ . . (undo)
(cur | prev) 20:21, 11 July 2017‎ David (talk | contribs)‎ . . (2,604 bytes) (-133)‎ . . (undo)
(cur | prev) 14:23, 11 July 2017‎ ChippyBot (talk | contribs)‎ m . . (2,737 bytes) (-11)‎ . . (Bot: Automated text replacement (-|avx512=Yes +)) (undo)
(cur | prev) 00:18, 7 July 2017‎ ChippyBot (talk | contribs)‎ m . . (2,748 bytes) (-68)‎ . . (package formatting change) (undo)
(cur | prev) 00:58, 30 June 2017‎ ChipIt (talk | contribs)‎ . . (2,816 bytes) (-1,985)‎ . . (undo)
(cur | prev) 13:02, 4 June 2017‎ ChipIt (talk | contribs)‎ . . (4,801 bytes) (0)‎ . . (undo)
(cur | prev) 11:07, 4 June 2017‎ ChipIt (talk | contribs)‎ . . (4,801 bytes) (+696)‎ . . (undo)
(cur | prev) 09:48, 4 June 2017‎ ChipIt (talk | contribs)‎ . . (4,105 bytes) (0)‎ . . (undo)
(cur | prev) 14:36, 26 May 2017‎ At32Hz (talk | contribs)‎ . . (4,105 bytes) (+755)‎ . . (more info from engineering samples) (undo)
(cur | prev) 02:31, 10 May 2017‎ David (talk | contribs)‎ . . (3,350 bytes) (+1)‎ . . (undo)
(cur | prev) 02:11, 10 May 2017‎ David (talk | contribs)‎ . . (3,349 bytes) (+395)‎ . . (undo)
(cur | prev) 01:23, 10 May 2017‎ David (talk | contribs)‎ . . (2,954 bytes) (+2,924)‎ . . (undo)
(cur | prev) 00:04, 10 May 2017‎ David (talk | contribs)‎ . . (30 bytes) (+30)‎ . . (Created page with "{{intel title|Xeon Gold 5122}}")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5122 - Intel#io +
base frequency	3,600 MHz (3.6 GHz, 3,600,000 kHz) +
chipset	Lewisburg +
clock multiplier	36 +
core count	4 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Gold +
first announced	April 25, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon gold/5122 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Transactional Synchronization Extensions +, Extended Page Tables + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	344.15 K (71 °C, 159.8 °F, 619.47 °R) +
max cpu count	4 +
max dts temperature	104 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	5122 +
name	Xeon Gold 5122 +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
part number	CD8067303330702 + and BX806735122 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
s-spec	SR3AT +
s-spec (qs)	QMRN +
series	5100 +
smp interconnect	UPI +
smp interconnect links	3 +
smp interconnect rate	10.4 GT/s +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas

Samsung