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== Members ==
 
== Members ==
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=== 5100/6100-Series (Skylake) ===
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=== Skylake ===
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{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
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{{see also|intel/microarchitectures/skylake|l1=Skylake µarch}}
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First-generation Xeon Gold processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the gold 5100/6100-series microprocessors feature four-way [[SMP]] capabilities with up to [[22 cores]] and 44 threads. Additionally, all Xeon Gold processors support:
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Introduced in July 2017, the {{intel|Skylake|l=arch}}-based Xeon Gold microprocessors support four-way [[multiprocessing]] with up to [[22 cores]] and 44 threads. Additionally, all Xeon Gold processors support:
  
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* '''Proc:''' [[14 nm process]]
 
 
* '''TDP:''' 85 W - 200 W
 
* '''TDP:''' 85 W - 200 W
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* '''Mem:''' 768 GiB hexa-channel DDR4-2400/2666 ECC memory.
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* '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory.
 
** ''M'' versions support 1.5 TiB per socket
 
** ''M'' versions support 1.5 TiB per socket
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* '''I/O:''' 48 PCIe Gen 3.0 lanes
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* '''I/O:''' 48 PCIe 3 lanes
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}})
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
 
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
  
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All Xeon Gold processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 3 {{intel|Ultra Path Interconnect}} (UPI) links. Note that the {{\|5122}} is the only 51xx SKU with a second FMA unit (on port 5) enabled.
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All Xeon Gold processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 3 {{intel|Ultra Path Interconnect}} (UPI) links.
  
 
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{{comp table start}}
 
{{comp table start}}
 
<table class="comptable sortable tc4 tc5">
 
<table class="comptable sortable tc4 tc5">
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{{comp table header|main|11:List of Skylake-based Xeon Gold Processors}}
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="20">List of Skylake-based Xeon Gold Processors</th></tr>
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{{comp table header|main|7:Main processor|2:Cache|2:Memory}}
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="7">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th></tr>
 
{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
 
{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
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{{comp table header|lsep|11:5100-Series}}
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Skylake]]
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Skylake (server)]][[series::5100]]
 
 
  |?full page name
 
  |?full page name
 
  |?model number
 
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}}
 
}}
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{{comp table header|lsep|11:6100-Series}}
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Skylake]]}}
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Skylake (server)]][[series::6100]]
 
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|?full page name
 
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|?model number
 
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|?release price
 
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|?first launched
 
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|?core count
 
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|?thread count
 
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|?base frequency#GHz
 
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|?turbo frequency (1 core)#GHz
 
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|?tdp
 
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|?l2$ size
 
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|?l3$ size
 
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|?supported memory type
 
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|?max memory#GiB
 
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}}
 
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Skylake (server)]]}}
 
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</table>
 
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{{comp table end}}
 
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=== 5200/6200-Series (Cascade Lake) ===
 
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{{see also|intel/microarchitectures/cascade lake|intel/cores/cascade lake sp|intel/cores/cascade lake r|l1=Cascade Lake µarch|l2=Cascade Lake SP corename|l3=Cascade Lake R corename}}
 
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Second-generation Xeon Scalable Gold was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 5200/6200-series Xeon Gold processors support:
 
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* '''Proc:''' [[14 nm process]]
 
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* '''TDP:''' 85 W - 200 W
 
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* '''Mem:''' 1 TiB hexa-channel DDR4-2400/2666 ECC memory
 
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** ''M'' versions support 2 TiB per socket
 
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** ''L'' versions support 4.5 TiB per socket
 
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* '''I/O:''' 48 PCIe Gen 3.0 lanes
 
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* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
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* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
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All Xeon Gold processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. Except for 'R' SKUs, all models also support 3 {{intel|Ultra Path Interconnect}} (UPI) links. Note that the {{\|5222}} is the only 51xx SKU with a second FMA unit (on port 5) enabled.
 
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          This table is generated automatically from the data in the actual articles.
 
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
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          created and tagged accordingly.
 
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
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-->
 
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{{comp table start}}
 
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<table class="comptable sortable tc4 tc5">
 
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{{comp table header|main|11:List of Cascade Lake-based Xeon Gold Processors}}
 
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{{comp table header|main|7:Main processor|2:Cache|2:Memory}}
 
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{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
 
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{{comp table header|lsep|11:5200-Series}}
 
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Cascade Lake]][[series::5200]]
 
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|?full page name
 
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|?model number
 
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|?release price
 
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|?first launched
 
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|?core count
 
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|?thread count
 
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|?base frequency#GHz
 
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|?turbo frequency (1 core)#GHz
 
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|?tdp
 
−
|?l2$ size
 
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|?l3$ size
 
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|?supported memory type
 
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|?max memory#GiB
 
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|format=template
 
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|template=proc table 3
 
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|valuesep=,
 
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|userparam=13
 
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|mainlabel=-
 
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}}
 
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{{comp table header|lsep|11:6200-Series}}
 
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{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Cascade Lake]][[series::6200]]
 
−
|?full page name
 
−
|?model number
 
−
|?release price
 
−
|?first launched
 
−
|?core count
 
−
|?thread count
 
−
|?base frequency#GHz
 
−
|?turbo frequency (1 core)#GHz
 
−
|?tdp
 
−
|?l2$ size
 
−
|?l3$ size
 
−
|?supported memory type
 
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|?max memory#GiB
 
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|format=template
 
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|template=proc table 3
 
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|valuesep=,
 
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|userparam=13
 
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|mainlabel=-
 
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}}
 
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{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Gold]] [[microarchitecture::Cascade Lake]]}}
 
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

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Facts about "Xeon Gold - Intel"
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designerIntel +
first announcedMay 4, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon gold +
instance ofmicroprocessor family +
instruction set architecturex86-64 +
main designerIntel +
manufacturerIntel +
microarchitectureSkylake +
nameXeon Gold +
packageFCLGA-3647 +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketLGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +