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Difference between revisions of "intel/xeon e7/e7-8850"
< intel‎ | xeon e7

(Memory controller)
(Features)
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== Features ==  
+
== Features ==
{{mpu features
+
{{x86 features
| em64t      = Yes
+
|real=Yes
| nx          = Yes
+
|protected=Yes
| txt        = Yes
+
|smm=Yes
| tsx        =  
+
|fpu=Yes
| vpro        =  
+
|x8616=Yes
| ht          = Yes
+
|x8632=Yes
| tbt1        = Yes
+
|x8664=Yes
| tbt2        =
+
|nx=Yes
| bpt        =  
+
|3dnow=No
| vt-x        = Yes
+
|e3dnow=No
| vt-d        = yes
+
|mmx=Yes
| ept        = Yes
+
|emmx=Yes
| mmx        = Yes
+
|sse=Yes
| sse         = Yes
+
|sse2=Yes
| sse2       = Yes
+
|sse3=Yes
| sse3       = Yes
+
|ssse3=Yes
| ssse3       = Yes
+
|sse41=Yes
| sse4.1      = Yes
+
|sse42=Yes
| sse4.2      = Yes
+
|sse4a=No
| aes        = Yes
+
|avx=No
| pclmul      =  
+
|avx2=No
| avx        =  
+
|avx512=No
| avx2        =  
+
|abm=No
| bmi        =  
+
|tbm=No
| bmi1       =  
+
|bmi1=No
| bmi2       =  
+
|bmi2=No
| f16c       =  
+
|fma3=No
| fma3        =  
+
|fma4=No
| mpx         =  
+
|aes=Yes
| sgx         =  
+
|rdrand=No
| eist        = Yes
+
|sha=No
| secure key  =  
+
|xop=No
| os guard    =  
+
|adx=No
| intel at    =  
+
|clmul=No
 +
|f16c=No
 +
|tbt1=Yes
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 
}}
 
}}

Revision as of 03:12, 2 December 2016

Template:mpu Xeon E7-8850 is a 64-bit deca-core x86 data center microprocessor that supports up to 8 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.4 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 4 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB4-way set associativewrite-back
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back

L2$2.56 MiB
2,621.44 KiB
2,684,354.56 B
0.0025 GiB
  10x256 KiB8-way set associativewrite-back

L3$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  10x2.4 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066
Supports ECCYes
Max Mem4 TiB
Controllers1
Channels4
Max Bandwidth31.77 GiB/s
32,532.48 MiB/s
34.113 GB/s
34,112.778 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 7.942 GiB/s
Double 15.88 GiB/s
Triple 23.83 GiB/s
Quad 31.77 GiB/s
Physical Address (PAE)44 bit

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AESAES Encryption Instructions
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 1.0Turbo Boost Technology 1.0
EISTEnhanced SpeedStep Technology
TXTTrusted Execution Technology (SMX)
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
Facts about "Xeon E7-8850 - Intel"
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 1 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description4-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.56 MiB (2,621.44 KiB, 2,684,354.56 B, 0.0025 GiB) +
l3$ description16-way set associative +
l3$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
max memory bandwidth31.77 GiB/s (32,532.48 MiB/s, 34.113 GB/s, 34,112.778 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels4 +
supported memory typeDDR3-1066 +