Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon e7/e7-4807"
(→Cache) |
|||
| Line 82: | Line 82: | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache = 384 KiB | ||
|l1i cache=192 KiB | |l1i cache=192 KiB | ||
|l1i break=6x32 KiB | |l1i break=6x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
| − | |l1i | + | |l1i policy=write-back |
|l1d cache=192 KiB | |l1d cache=192 KiB | ||
|l1d break=6x32 KiB | |l1d break=6x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=1.5 MiB | |l2 cache=1.5 MiB | ||
|l2 break=6x256 KiB | |l2 break=6x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=18 MiB | |l3 cache=18 MiB | ||
| + | |l3 break=6x3 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 01:31, 2 December 2016
Template:mpu Xeon E7-4807 is a 64-bit hexa-core x86 data center microprocessor that supports up to 4 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.86 GHz with 95 W TDP but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3-800 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max memory | 2048 GB |
Features
Facts about "Xeon E7-4807 - Intel"
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
