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Difference between revisions of "intel/xeon e5/e5-4627 v4"
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{{intel title|Xeon E5-4627 v4}} | {{intel title|Xeon E5-4627 v4}} | ||
− | {{ | + | {{chip |
| name = Xeon E5-4627 v4 | | name = Xeon E5-4627 v4 | ||
| no image = Yes | | no image = Yes | ||
Line 10: | Line 10: | ||
| model number = E5-4627 v4 | | model number = E5-4627 v4 | ||
| part number = CM8066002330800 | | part number = CM8066002330800 | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Server | | market = Server | ||
| first announced = June 20, 2016 | | first announced = June 20, 2016 | ||
Line 34: | Line 34: | ||
| s-spec = SR2SN | | s-spec = SR2SN | ||
| s-spec es = | | s-spec es = | ||
− | | s-spec qs = | + | | s-spec qs = QKSZ |
| cpuid = 406F1 | | cpuid = 406F1 | ||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
| microarch = Broadwell | | microarch = Broadwell | ||
| platform = Grantley EP 4S | | platform = Grantley EP 4S | ||
Line 54: | Line 56: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
− | + | ||
| v core = 1.82 V | | v core = 1.82 V | ||
| v core tolerance = | | v core tolerance = | ||
Line 83: | Line 85: | ||
| socket 0 type = LGA | | socket 0 type = LGA | ||
}} | }} | ||
− | The '''Xeon E5-4627 v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.6 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | + | The '''Xeon E5-4627 v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.6 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). This specific model has no hyper-threading enabled. |
== Cache == | == Cache == | ||
Line 120: | Line 122: | ||
| max memory = 1,536 GiB | | max memory = 1,536 GiB | ||
| pae = 46 bit | | pae = 46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 40 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = Yes | ||
+ | | vpro = | ||
+ | | ht = | ||
+ | | tbt1 = | ||
+ | | tbt2 = Yes | ||
+ | | tbmt3 = | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = Yes | ||
+ | | ept = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | pclmul = Yes | ||
+ | | avx = Yes | ||
+ | | avx2 = Yes | ||
+ | | bmi = Yes | ||
+ | | bmi1 = Yes | ||
+ | | bmi2 = Yes | ||
+ | | f16c = Yes | ||
+ | | fma3 = Yes | ||
+ | | mpx = | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = Yes | ||
+ | | os guard = Yes | ||
+ | | intel at = | ||
+ | | intel ipt = | ||
}} | }} |
Latest revision as of 16:28, 13 December 2017
Edit Values | |
Xeon E5-4627 v4 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | E5-4627 v4 |
Part Number | CM8066002330800 |
S-Spec | SR2SN QKSZ (QS) |
Market | Server |
Introduction | June 20, 2016 (announced) June 20, 2016 (launched) |
Release Price | $2225 |
Shop | Amazon |
General Specs | |
Family | Xeon E5 |
Series | E5-4000 |
Locked | Yes |
Frequency | 2,600 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 3,200 MHz (1 core) |
Bus type | QPI |
Bus speed | 4,000 MHz |
Bus rate | 2 × 8 GT/s |
Clock multiplier | 26 |
CPUID | 406F1 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grantley EP 4S |
Chipset | C610 Series |
Core Name | Broadwell EP |
Core Family | 6 |
Core Model | 4F |
Core Stepping | M0 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 10 |
Threads | 10 |
Max Memory | 1,536 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Electrical | |
Vcore | 1.82 V |
VI/O | 1.2 V ± 3% |
TDP | 135 W |
Tcase | 0 °C – 82 °C |
Tstorage | -25 °C – 125 °C |
The Xeon E5-4627 v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.6 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell). This specific model has no hyper-threading enabled.
Cache[edit]
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
L2$ | 2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB |
10x256 KiB 8-way set associative (per core, write-back) |
L3$ | 25 MiB 25,600 KiB 26,214,400 B 0.0244 GiB |
10x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics[edit]
This microprocessor has no integrated graphics processing unit.
Memory controller[edit]
Integrated Memory Controller | |
Type | DDR4-2133 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 63.58 GiB/s |
Bandwidth (single) | 15.89 GiB/s |
Bandwidth (dual) | 31.79 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Xeon E5-4627 v4 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) + |