From WikiChip
Difference between revisions of "intel/xeon e5/e5-2680 v4"
< intel‎ | xeon e5

(→‎Memory controller)
(+features)
Line 120: Line 120:
 
| max memory        = 1,536 GiB
 
| max memory        = 1,536 GiB
 
| pae                = 46 bit
 
| pae                = 46 bit
 +
}}
 +
 +
== Features ==
 +
{{mpu features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2      = Yes
 +
| aes        = Yes
 +
| pclmul      = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard    = Yes
 +
| intel at    =
 +
| intel ipt  =
 
}}
 
}}

Revision as of 19:23, 3 November 2016

Template:mpu The Xeon E5-2680 v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 2S environments. Operating at 2.4 GHz with a turbo boost frequency of 3.3 GHz for a single active core, this MPU has a TDP of 120 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L1D$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L2$ 3.5 MiB
3,584 KiB
3,670,016 B
0.00342 GiB
14x256 KiB 8-way set associative (per core, write-back)
L3$ 35 MiB
35,840 KiB
36,700,160 B
0.0342 GiB
14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2680_v4&oldid=26664"
Facts about "Xeon E5-2680 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +